FinFET devices

Patent metadata

Field	Value
Publication number	US-9685507-B2
Application number	US-201514750013-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

First claim

What is claimed:

1. A method comprising:
forming a first set of trenches in a semiconductor material;
filling the first set of trenches with insulator material;
forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled, the second set of trenches forming semiconductor structures which have a dimension of fin structures;
filling the second set of trenches with insulator material; and
recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures wherein:
forming the first set of trenches comprises:
forming a plurality of mandrels on an insulator layer;
forming sidewall spacers on the plurality of mandrels;
removing the plurality of mandrels, leaving a space between the sidewall spacers; and
etching into the semiconductor material within the space between the sidewall spacers; and

forming the second set of trenches comprises:
removing the sidewall spacers;
forming inner sidewall spacers on upper portions of the insulator material that filled the first set of trenches;
etching into the semiconductor material within spaces between adjacent ones of the inner sidewall spacers.

2. The method of claim 1 , wherein the insulator material in the first set of trenches and the second set of trenches is oxide material.

3. The method of claim 1 , wherein the filling of the first set of trenches and the second set of trenches includes a flowable oxide followed by an anneal process.

4. The method of claim 1 , wherein the fin structures are partially supported by the insulator material at a bottom portion thereof.

5. The method of claim 1 , further comprising removing the inner sidewalls spacers.

6. The method of claim 1 , wherein the inner sidewall spacers include a dimension of the fin structures.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title