Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Patent metadata

Field	Value
Publication number	US-9685390-B2
Application number	US-201213994521-A
Country	US
Kind code	B2
Filing date	Jun 8, 2012
Priority date	Jun 8, 2012
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar). The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

First claim

What is claimed is:

1. A microelectronic package, comprising:
an encapsulated structure including a plurality of microelectronic devices having active surfaces substantially encapsulated within an encapsulation material, wherein the encapsulated structure includes an active surface proximate the microelectronic device active surfaces, and wherein at least one of the plurality of microelectronic devices has a height greater than another of the plurality of microelectronic devices;
at least one microelectronic device that is not encapsulated within the encapsulation material positioned proximate the encapsulated structure active surface and electrically connected to at least one of the plurality of microelectronic devices of the encapsulated structure through at least one bond wire; and
a bumpless build-up layer structure formed on the encapsulated structure active surface, wherein a first dielectric layer of the bumpless build-up layer structure substantially encapsulates the at least one microelectronic device that is not encapsulated within the encapsulation material.

2. The microelectronic package of claim 1 , wherein the at least one microelectronic device that is not encapsulated within the encapsulation material is electrically connected to at least one of the plurality of microelectronic devices of the encapsulated structure through the bumpless build-up layer structure.

3. The microelectronic package of claim 1 , further comprising external interconnects electrically connected to the bumpless build-up layer structure.

4. The microelectronic package of claim 1 , wherein at least one of the plurality of microelectronic devices of the encapsulated structure includes at least one connection structure extending from the active surface thereof, and wherein the encapsulation material does not encapsulate the at least one connection structure of the at least one of the plurality of microelectronic devices of the encapsulated structure.

5. The microelectronic package of claim 1 , wherein the encapsulation material comprises a silica-filled epoxy.

6. A microelectronic package, comprising:
an encapsulated structure including a plurality of microelectronic devices having active surfaces substantially encapsulated within an encapsulation material, wherein the encapsulated structure includes an active surface proximate the microelectronic device active surfaces, wherein at least one of the plurality of microelectronic devices has a height greater than another of the plurality of microelectronic devices, wherein the encapsulated structure further comprises a back surface, wherein the encapsulated structure back surface is substantially co-planar with a back surface of at least one of the plurality of microelectronic devices of the encapsulated structure having the greatest height;
at least one microelectronic device that is not encapsulated within the encapsulation material positioned proximate the encapsulated structure active surface; and
a bumpless build-up layer structure formed on the encapsulated structure active surface, wherein a first dielectric layer of the bumpless build-up layer structure substantially encapsulates the at least one microelectronic device that is not encapsulated within the encapsulation material and wherein the at least one microelectronic device that is not encapsulated is electrically connected to at least one of the plurality of microelectronic devices of the encapsulated structure through at least one bond wire.

7. The microelectronic package of claim 6 , wherein the encapsulation material comprises a silica-filled epoxy.

Assignees

• Hu Chuan
• Intel Corp

Inventors

• Hu Chuan

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title