Photomask for forming multiple layer patterns with a single exposure

Patent metadata

Field	Value
Publication number	US-9685367-B2
Application number	US-201615394466-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	May 14, 2013
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a mask, wherein the mask includes:
a first mask material layer over a mask substrate and patterned to have a first plurality of openings that define a first layer pattern; and
a second mask material layer over the first mask material layer and patterned to have a second plurality of openings that define a second layer pattern;

providing a target substrate having a first photoresist layer and a second photoresist layer over the first photoresist layer; and
performing a lithography exposure by patterning a radiation beam using the provided mask, wherein the first layer pattern is formed on to the first photoresist layer and the second layer pattern is formed on the second photoresist layer.

2. The method of claim 1 , wherein the providing the target substrate including providing the first photoresist layer and the second photoresist layer of a positive tone.

3. The method of claim 1 , wherein the providing the target substrate includes providing the first photoresist layer of a first exposure threshold and providing the second photoresist layer of a second exposure threshold, wherein the first and second exposure thresholds are different.

4. The method of claim 3 , wherein the second exposure threshold is lower than the first exposure threshold.

5. The method of claim 1 , wherein the lithography exposure exposes a latent pattern associated with the second layer pattern on the first photoresist layer, the latent pattern formed with an intensity below an exposure threshold of the first photoresist layer.

6. The method of claim 5 , further comprising:
developing the first photoresist layer, wherein the first layer pattern is defined after development and the second layer pattern is not defined on the first photoresist layer.

7. The method of claim 1 , wherein the lithography exposure defines a latent pattern associated with the first layer pattern on the second photoresist layer, the latent pattern formed with an intensity above an exposure threshold of the second photoresist layer.

8. A method of fabricating a semiconductor device, the method comprising:
providing a mask, wherein the mask includes:
a first mask material layer over a mask substrate and patterned with a first layer pattern of an integrated circuit (IC); and
a second mask material layer over the first mask material layer and patterned with a second layer pattern of the IC, wherein the first and second layer patterns are different patterns of features of the IC;

providing a semiconductor substrate having a first photoresist layer and a second photoresist layer over the first photoresist layer, wherein the first and second photoresist layers have a different exposure threshold; and
performing a lithography exposure process to the first photoresist layer and the second photoresist layer, thereby forming a first feature of the first layer pattern in the first photoresist layer and a second feature of the second layer pattern in the second photoresist layer.

9. The method of claim 8 , wherein the first feature is a via feature.

10. The method of claim 9 , wherein the second feature is a line feature.

11. The method of claim 8 , further comprising:
developing the first feature of the first photoresist layer; and
developing the second feature of the second photoresist layer.

12. The method of claim 11 , further comprising: performing at least one etching step between the developing the first feature and the developing the second feature.

13. The method of claim 11 , further comprising:
using the first feature as a masking element to define a via in a first dielectric layer; and
using the second feature as a masking element to define a trench in a second dielectric layer over the first dielectric layer.

14. The method of claim 13 , further comprising:
filling the via and the trench with conductive material.

15. A method of semiconductor device fabrication, the method comprising:
providing a semiconductor substrate having a first photoresist layer and an overlying second photoresist layer;
providing a mask having a first layer defining a first pattern and a second layer defining a second pattern, the second pattern different than the first pattern;
using the mask, concurrently exposing the first and the second photoresist layers to form a first latent feature defined by the first pattern on the first photoresist layer and a second latent feature defined by the second pattern on the second photoresist layer;
applying a first developer to develop the second photoresist layer to form a first feature from the second latent feature;
after applying the first developer, applying a second developer, different than the first developer, to develop the first photoresist layer to form a second feature from the first latent feature.

16. The method of claim 15 , further comprising:
using the first feature as a masking element while etching a first dielectric layer.

17. The method of claim 16 , further comprising:
using the second feature as a masking element while etching a second dielectric layer.

18. The method of claim 17 , wherein the etching the first dielectric layer and the second dielectric layer provides a continuous opening defined by the first and second features.

19. The method of claim 18 , further comprising:
filling the continuous opening with a conductive material.

20. The method of claim 15 , wherein the first photoresist layer is indissoluble in the first developer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Yen-Cheng
• Shih Chih-Tsung
• Yu Shinn-Sheng
• Chen Jeng-Horng
• Yen Anthony

Classifications

• H10P76/2045

  Electron beam lithography processes · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title