Memory device with over-refresh and method thereof

Patent metadata

Field	Value
Publication number	US-9685217-B2
Application number	US-201313947826-A
Country	US
Kind code	B2
Filing date	Jul 22, 2013
Priority date	Jul 22, 2013
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

In a method, error detection and correction is performed on output data from a memory cell of a memory device to generate a result of error detection and correction. The memory cell is determined as a weak cell by determining a number of times of data retention failures of the memory cell based on the result of the error detection and correction. In a refreshing cycle, normal cells and the weak cell are refreshed and the weak cell is additionally refreshed at least once.

First claim

What is claimed is:

1. A method, comprising:
performing error detection and correction on output data from a memory cell of a memory device to generate a result of error detection and correction;
determining the memory cell as a weak cell in response to a predetermined number of times of data retention failures of the memory cell based on the result of the error detection and correction;
in a first clock cycle, reading data stored in the weak cell based on a first address of the weak cell provided by a system controller;
performing error detection and correction on the data to obtain error corrected data;
in a second clock cycle, writing the error corrected data into the weak cell based on the first address; and
in a refreshing cycle,
refreshing normal cells and the weak cell of the memory device based on a plurality of corresponding second addresses of the normal cells and the weak cell provided by a refresh controller; and
additionally refreshing the weak cell at least once based on a third address of the weak cell provided by the refresh controller.

2. The method according to claim 1 , wherein
the second clock cycle is consecutive to the first clock cycle.

3. The method according to claim 2 , further comprising:
in one of the first clock cycle and the second clock cycle, extracting the first address to obtain the third address.

4. The method according to claim 1 , wherein
the second clock cycle and the first clock cycle are separated in time.

5. The method according to claim 4 , further comprising:
in the second clock cycle, extracting the first address to obtain the third address.

6. The method according to claim 1 , wherein in the refreshing cycle, refreshing the normal cells and the weak cell and additionally refreshing the weak cell comprise:
based on a plurality of address portions in the plurality of second addresses, portion-by-portion, refreshing cells in each address portion along with refreshing the weak cell.

7. A system, comprising:
a memory block comprising normal cells and a weak cell;
a system controller;
an error correction code (ECC) capability; and
a refresh controller;
the system controller being configured to provide a first address of the weak cell;
the memory block being configured to read data stored in the weak cell in a first clock cycle based on the first address;
the ECC capability being configured to perform error detection and correction on the data to obtain error corrected data;
the memory block being further configured to write the error corrected data into the weak cell in a second clock cycle based on the first address; and
the refresh controller being configured to provide a plurality of corresponding second addresses of the normal cells and the weak cell based on which the normal cells and the weak cell are refreshed once in a refreshing cycle, and to provide a third address of the weak cell based on which the weak cell is additionally refreshed at least once in the refreshing cycle.

8. The system according to claim 7 , wherein
the second clock cycle is consecutive to the first clock cycle.

9. The system according to claim 8 , wherein
the refresh controller comprises an address-extracting device configured to extract the first address in response to an assertion of a signal; and
the signal is asserted in the first clock cycle or the second clock cycle.

10. The system according to claim 7 , wherein
the second clock cycle and the first clock cycle are separated in time.

11. The system according to claim 10 , wherein
the refresh controller comprises an address-extracting device configured to extract the first address in response to an assertion of a signal; and
the signal is asserted in the second clock cycle.

12. The system according to claim 7 , wherein the refresh controller further comprises:
a refresh address counter configured to output the plurality of second addresses in the refreshing cycle;
an address-extracting device configured to extract the first address to obtain the third address;
a multiplexer configured to select one address of the plurality of second addresses from the refresh address counter or the third address from the address-extracting device for refreshing,
wherein
the refresh controller controls the multiplexer and the refresh address counter such that the multiplexer selects the address-extracting device at least once in the refreshing cycle.

13. The system according to claim 12 , wherein the refresh controller is configured to control the refresh address counter and the multiplexer such that based on a plurality of address portions in the plurality of second addresses, portion-by-portion, the multiplexer selects the refresh address counter to output addresses of each address portion, and selects the address-extracting device to output the third address.

14. A method, comprising:
in a first clock cycle, reading data stored in a weak cell of a memory device based on a first address of the weak cell provided by a system controller;
performing error detection and correction on the data to obtain error corrected data;
in a second clock cycle, writing the error corrected data into the weak cell based on the first address; and
in a refreshing cycle,
refreshing normal cells and the weak cell of the memory device based on a plurality of corresponding second addresses of the normal cells and the weak cell provided by a refresh controller; and
additionally refreshing the weak cell at least once based on a third address of the weak cell provided by the refresh controller.

15. The method according to claim 14 , wherein
the second clock cycle is consecutive to the first clock cycle.

16. The method according to claim 15 , further comprising:
in one of the first clock cycle and the second clock cycle, extracting the first address to obtain the third address.

17. The method according to claim 14 , wherein
the second clock cycle and the first clock cycle are separated in time.

18. The method according to claim 17 , further comprising:
in the second clock cycle, extracting the first address to obtain the third address.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Romanovskyy Sergiy
• Oconnell Cormac Michael

Classifications

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1008

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title