Translation lookaside buffer invalidation suppression

Patent metadata

Field	Value
Publication number	US-9684606-B2
Application number	US-201414541726-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.

First claim

What is claimed is:

1. A method for managing a plurality of translation lookaside buffers, each translation lookaside buffer including a plurality of translation lookaside buffer entries and being associated with a corresponding processing element of a plurality of processing elements, the method comprising:
issuing, at a first processing element of the plurality of processing elements, a first instruction for invalidating one or more translation lookaside buffer entries associated with a first context in a first translation lookaside buffer associated with the first processing element, the issuing including:
determining, at the first processing element, whether or not a state of an indicator indicates that all translation lookaside buffer entries associated with the first context in a second translation lookaside buffer associated with a second processing element are invalidated;
if the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated:
sending a corresponding instruction to the second processing element of the plurality of processing elements, the corresponding instruction causing invalidation of all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer while maintaining one or more translation lookaside buffer entries associated with one or more other contexts in the second translation lookaside buffer, and
changing a state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are invalidated; and

if the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer associated with the second processing element are invalidated:
suppressing sending of any corresponding instructions for causing invalidation of any translation lookaside buffer entries associated with the first context in the second translation lookaside buffer to the second processing element.

2. The method of claim 1 further comprising, prior to determining whether or not the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are invalidated,
determining whether a second context associated with the indicator is the same as the first context associated with the first instruction; and
if the second context differs from the first context, changing the state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated.

3. The method of claim 1 further comprising issuing a synchronization instruction at the first processing element, the synchronization instruction causing any pending translation lookaside buffer invalidation instructions at the first processing element to complete and, upon their completion, changing the state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated.

4. The method of claim 1 further comprising,
determining, at the first processing element, whether or not a state of the indicator indicates that all translation lookaside buffer entries associated with the first context in a plurality of other translation lookaside buffers corresponding to a plurality of other processing elements of the plurality of processing elements are invalidated; and
if the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the plurality of other translation lookaside buffers are not invalidated,
sending the corresponding instruction to the plurality of other processing elements, the corresponding instruction causing invalidation of all translation lookaside buffer entries associated with the first context in the plurality of other translation lookaside buffers; and

if the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the plurality of other translation lookaside buffers are invalidated:
suppressing sending of any corresponding instructions for causing invalidation of any translation lookaside buffer entries associated with the first context in the plurality of other translation lookaside buffers to the second processing element.

5. The method of claim 1 further comprising generating the corresponding instruction including converting the first instruction for invalidating one or more translation lookaside buffer entries associated with the first context in the first translation lookaside buffer to the corresponding instruction for causing invalidation of all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer.

6. The method of claim 1 wherein the state of the indicator is represented using a single bit.

7. The method of claim 1 wherein the first context includes an address space identifier (ASID).

8. The method of claim 1 wherein the first context includes a virtual machine identifier (VMID).

9. The method of claim 1 wherein the first context includes an exception level (EL).

10. The method of claim 1 further comprising receiving a synchronization message and changing the state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated in response to the synchronization message.

11. The method of claim 1 further comprising receiving an interrupt and changing the state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated in response to receiving the interrupt.

12. An apparatus comprising:
a plurality of processing elements, each associated with a corresponding translation lookaside buffer, each translation lookaside buffer including a plurality of translation lookaside buffer entries;
wherein a first processing element of the plurality of processing elements is configured to issue a first instruction for invalidating one or more translation lookaside buffer entries associated with a first context in a first translation lookaside buffer associated with the first processing element, the issuing including:
determining, at the first processing element, whether or not a state of an indicator indicates that all translation lookaside buffer entries associated with the first context in a second translation lookaside buffer associated with a second processing element are invalidated;
if the state of the indicator indicates that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are not invalidated:
sending a corresponding instruction to the second processing element of the plurality of processing elements, the corresponding instruction causing invalidation of all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer while maintaining one or more translation lookaside buffer entries associated with one or more other contexts in the second translation lookaside buffer, and
changing a state of the indicator to indicate that all translation lookaside buffer entries associated with the first context in the second translation lookaside buffer are invalidated; and

Assignees

• Cavium Inc

Inventors

• Kessler Richard Eugene
• Mukherjee Shubhendu Sekhar
• Bertone Mike

Classifications

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title