Memory address generation for digital signal processing

Patent metadata

Field	Value
Publication number	US-9684592-B2
Application number	US-201615357682-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Aug 30, 2012
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.

First claim

What is claimed is:

1. A processing system, comprising:
a first memory storing a plurality of data items arranged in a first sequence, each data item having an associated memory address on the first memory;
at least one processor coupled to the first memory and arranged to read and write data directly to the first memory; and
a direct memory access controller coupled to the first memory, and including:
a port to a second memory, and
a configurable address generator arranged to compute a sequence of read addresses according to a selected one of a plurality of different read modes and to compute a sequence of write addresses according to a selected one of a plurality of different write modes;

wherein the computed sequence of read addresses and the computed sequence of write addresses are combined such that the direct memory access controller is configured to transfer the plurality of data items directly from the first memory to the second memory using the computed sequence of read addresses and the computed sequence of write addresses, such that the data items written to the second memory during the transfer are arranged in a second sequence that is different from the first sequence, and
wherein a read mode is a pattern in which data items are read from memory in a single transaction and a write mode is a pattern in which data items are written to memory in a single transaction.

2. The processing system according to claim 1 , wherein the direct memory access controller is configured to read a data item associated with the first address in the sequence of read addresses; perform an operation on the data item to generate a processed data item; write that processed data item to the first address in the sequence of write addresses; and repeat said reading, performing an operation and writing for each subsequent address in the sequence of read addresses and write addresses.

3. The processing system according to claim 2 , wherein the direct memory access controller is configured to perform an operation on the data item to generate a processed data item by:
providing the data item to one or more hardware peripherals for processing.

4. The processing system according to claim 1 , wherein the selected one of the plurality of read modes is arranged to configure the address generator to cause the direct memory access controller to read the data items from a non-linear sequence of memory addresses on the first memory, and the selected one of the plurality of write modes is arranged to configure the address generator to cause the direct memory access controller to write the data items to a linear sequence of addresses on the second memory.

5. The processing system according to claim 1 , wherein the selected one of the plurality of read modes is arranged to configure the address generator to cause the direct memory access controller to read the data items from a linear sequence of memory addresses on the first memory, and the selected one of the plurality of write modes is arranged to configure the address generator to cause the direct memory access controller to write the data items to a non-linear sequence of addresses on the second memory.

6. The processing system according to claim 1 , wherein the selected one of the plurality of read modes is arranged to configure the address generator to cause the direct memory access controller to read the data items from a non-linear sequence of memory addresses on the first memory, and the selected one of the plurality of write modes is arranged to configure the address generator to cause the direct memory access controller to write the data items to a non-linear sequence of addresses on the second memory.

7. The processing system according to claim 1 , wherein the direct memory access controller is further configured to transfer the plurality of data items directly from the second memory to the first memory, and the address generator is arranged to compute a further sequence of read addresses according to a further selected one of a plurality of read modes and to compute a further sequence of write addresses according to a further selected one of a plurality of write modes, such that the data items written to the first memory during the transfer from the second memory to the first memory are arranged in a third sequence that is different from the first and second sequence.

8. The processing system according to claim 1 , wherein the second memory is a dynamic random access memory.

9. The processing system according to claim 1 , wherein the first memory is a static random access memory.

10. The processing system according to claim 1 , further comprising a control processor arranged to execute a program configured to select the one of the plurality of read modes and the one of the plurality of write modes for use by the address generator and provide these selections to the address generator.

11. The processing system according to claim 1 , wherein the processing system further comprises a plurality of hardware peripherals, each connected to the direct memory access controller and each configured to read data from the first memory via the direct memory access controller, perform one or more operations on the data, and write data to the first memory device via the direct memory access controller.

12. The processing system according to claim 1 , wherein the plurality of data items in the first sequence are defined as being arranged as a grid of elements having a plurality of rows and columns, each element comprising a group of consecutive data items from the first sequence.

13. The processing system according to claim 1 , wherein the plurality of data items in the first sequence are defined as being arranged as a grid having a plurality of rows and columns.

14. The processing system according to claim 13 , wherein the selected one of the plurality of read modes and the selected one of the plurality of write modes together configure the address generator to manipulate the memory address of each data item such that the second sequence is based on a transpose of the grid.

15. The processing system according to claim 13 , wherein the selected one of the plurality of read modes and the selected one of the plurality of write modes together configure the address generator to manipulate the memory address of each data item such that the second sequence is based on a transpose of the grid with a position shift applied to the elements of one or more columns or rows.

16. The processing system according to claim 1 , wherein the selected one of the plurality of read modes and the selected one of the plurality of write modes together configure the address generator to manipulate the memory address associated with each data item during the transfer such that the second sequence is equivalent to at least a portion of a convolutional de-interleaving operation performed on the first sequence.

17. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system comprising:
at least one digital signal processor coupled to a first memory and arranged to read and write data directly to the first memory, wherein the first memory is arranged to store a plurality of data items arranged in a first sequence, each data item having an associated memory address on the first memory; and
a direct memory access controller coupled to the first memory, and including:
a port to a pa

Assignees

• Imagination Tech Ltd

Inventors

• Anderson Adrian J

Classifications

• G06F12/063 Primary

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• H03M13/2764

  Circuits therefore · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title