Systems and methods of low power clocking for sleep mode radios

US9680413B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9680413-B2
Application numberUS-201213406849-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2012
Priority dateFeb 28, 2012
Publication dateJun 13, 2017
Grant dateJun 13, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.

First claim

Opening claim text (preview).

Therefore, at least the following is claimed: 1. A communications apparatus, comprising: a real time unit configured for tracking real time based on a first clock; application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode; a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock; a low-power low-accuracy oscillator (LPLAO) crystal oscillator mistuned by loading with a smaller capacitance than used for correctly tuning said LPLAO and configured to provide said first clock, said LPLAO purposely mistuned to provide said first clock using less power but with less accuracy than if correctly tuned; and a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing. 2. The apparatus of claim 1 , wherein said smaller capacitance is a parasitic capacitance experienced by said crystal oscillator. 3. A communications apparatus, comprising: a real time unit configured for tracking real time based on a first clock; application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode; a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock; a low-power low-accuracy resistor-capacitor (RC) oscillator configured to compensate offset voltages at inputs of a comparator in said RC oscillator and configured to provide said first clock, said low-power low-accuracy resistor-capacitor (RC) oscillator purposely mistuned to provide said first clock using less power but with less accuracy than if correctly tuned; and a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing. 4. The apparatus of claim 3 , wherein a resistor-capacitor combination of the RC oscillator is switched into connection with said comparator inputs alternatingly with each switching phase of the RC oscillator. 5. The apparatus of claim 4 , wherein, in a first said switching phase, a first said offset voltage causes an increase in propagation delay and, in a second said switching phase, a second said offset voltage causes a decrease in propagation delay. 6. The apparatus of claim 5 , wherein said first and second offset voltages are substantially equal and said increase and decrease in propagation delay are substantially equal.

Assignees

Inventors

Classifications

  • with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator · CPC title

  • being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title

  • Details · CPC title

  • the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

  • H03B5/26Primary

    frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9680413B2 cover?
Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operati…
Who is the assignee on this patent?
Paidimarri Arun, Griffith Danielle, Wang Alice, and 1 more
What technology area does this patent fall under?
Primary CPC classification H03B5/26. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).