Systems and methods of low power clocking for sleep mode radios

Patent metadata

Field	Value
Publication number	US-9853651-B2
Application number	US-201715430182-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Feb 28, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Systems and methods of low power docking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.

First claim

The invention claimed is:

1. A communications apparatus, comprising:
a real time unit configured for tracking real time based on a first clock;
application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock;
a low-power low-accuracy oscillator (LPLAO) purposely mistuned by lowering a load capacitance of the LPLAO to be less than what is required for the LPLAO to operate at a specified frequency for the first clock; and
a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.

2. The apparatus of claim 1 , wherein said comparing occurs at regular intervals.

3. The apparatus of claim 1 , wherein said real time unit and said application circuitry and said high-accuracy oscillator and said calibration unit are provided in a communications node; and wherein said LPLAO is externally coupled to said communications node.

4. The apparatus of claim 1 , wherein said comparing and said adjusting occur during said sleep mode.

5. The apparatus of claim 4 , wherein said comparing and said adjusting occur at selected intervals.

6. The apparatus of claim 1 , wherein said high-accuracy oscillator is active during said sleep mode only at said selected intervals.

7. The apparatus of claim 1 , wherein said comparing and said adjusting occur at selected intervals.

8. A method of operating a communications apparatus, comprising:
tracking real time based on a first clock provided by a low-power low-accuracy oscillator (LPLAO) purposely mistuned by lowering a load capacitance of the LPLAO to be less than what is required for the LPLAO to operate at a specified frequency for the first clock to provide said first clock using less power but with less accuracy than if correctly tuned for said specified frequency;
during an operational mode, executing a communications application based on a second clock provided by a high-accuracy oscillator at a frequency that is higher than a frequency of said first clock;
entering a sleep mode for a period of real time measured by said tracking;
comparing said first clock to said second clock; and
adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.

9. The method of claim 8 , wherein said comparing and said adjusting occur during said sleep mode.

10. The method of claim 9 , wherein said comparing and said adjusting occur at selected intervals.

11. The method of claim 10 , including activating the high-accuracy oscillator during said sleep mode only at said selected intervals.

12. The method of claim 8 , wherein said comparing and said adjusting occur at selected intervals.

13. A communications apparatus, comprising:
a real time unit configured for tracking real time based on a first clock;
application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock;
an oscillator purposely mistuned by lowering a load capacitance of the oscillator to be less than what is required for the oscillator to operate at a specified frequency for the first clock; and
a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.

14. The apparatus of claim 13 , wherein said comparing occurs at regular intervals.

15. The apparatus of claim 13 , wherein said real time unit and said application circuitry and said high-accuracy oscillator and said calibration unit are provided in a communications node, and wherein said oscillator is externally coupled to said communications node.

16. The apparatus of claim 13 , wherein said comparing and said adjusting occur during said sleep mode.

17. The apparatus of claim 16 , wherein said comparing and said adjusting occur at selected intervals.

18. The apparatus of claim 13 , wherein said high-accuracy oscillator is active during said sleep mode only at said selected intervals.

19. The apparatus of claim 13 , wherein said comparing and said adjusting occur at selected intervals.

20. A method of operating a communications apparatus, comprising:
tracking real time based on a first dock;
executing a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
providing said second clock at a frequency that is higher than a frequency of said first clock;
purposely mistuning an oscillator by lowering a load capacitance of the oscillator to be less than what is required for the oscillator to operate at a specified frequency for the first clock; and
comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.

21. The method of claim 20 , wherein said comparing and said adjusting occur during said sleep mode.

22. The method of claim 21 , wherein said comparing and said adjusting occur at selected intervals.

23. The method of claim 22 , including activating the high-accuracy oscillator during said sleep mode only at said selected intervals.

24. The method of claim 20 , wherein said comparing and said adjusting occur at selected intervals.

25. The method of claim 20 , wherein the oscillator is a low-power low-accuracy oscillator (LPLAO).

Assignees

• Texas Instruments Inc

Inventors

• Paidimarri Arun
• Griffith Danielle
• Wang Alice

Classifications

• H03B1/00

  Details · CPC title

• H03B5/24

  active element in amplifier being semiconductor device (H03B5/26 takes precedence) · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03B5/32

  being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title

• H03B5/20

  with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator · CPC title