Bi-directional punch-through semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9679998-B2
Application number	US-201615088297-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 10, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

First claim

What is claimed is:

1. A bi-directional punch-through semiconductor device, comprising:
a) a first transistor in a first region of a semiconductor substrate of a first conductivity type, wherein said first transistor comprises a semiconductor buried layer of a second conductivity type in said semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above said semiconductor buried layer, said semiconductor buried layer being configured as a base of said first transistor; and
b) a second transistor coupled in parallel with said first transistor, wherein said second transistor is in a second region of said semiconductor substrate of said first conductivity type, wherein said second transistor comprises a second epitaxy region of said epitaxy semiconductor layer above said semiconductor substrate, and a first doped region of said second conductivity type in said second epitaxy region, said first doped region being configured as a base of said second transistor, and wherein said first and second epitaxy regions have different conductivity types.

2. The semiconductor device of claim 1 , wherein said first and second epitaxy regions are respectively auto-doped by said semiconductor buried layer and said semiconductor substrate.

3. The semiconductor device of claim 1 , wherein said first epitaxy region is of said second conductivity type.

4. The semiconductor device of claim 1 , wherein said second epitaxy region is one of an intrinsic characteristic or said first conductivity type.

5. The semiconductor device of claim 1 , wherein said first transistor further comprises a second doped region of said first conductivity type in said first epitaxy region, and said second transistor further comprises a third doped region of said first conductivity type in said first doped region.

6. The semiconductor device of claim 5 , further comprising:
a) a first PN junction formed between said semiconductor buried layer and said semiconductor substrate;
b) a second PN junction formed between said first epitaxy region and said second doped region;
c) a third PN junction formed between said first and third doped regions; and
d) a fourth PN junction formed between said first doped region and said second epitaxy region.

7. The semiconductor device of claim 6 , wherein said punch-through occurs instead of avalanche breakdown when said first and third PN junctions withstand a reverse voltage higher than a breakdown voltage.

8. The semiconductor device of claim 7 , wherein said first PN junction is punched through by regulating the doping concentration of said semiconductor buried layer and said epitaxy semiconductor layer.

9. The semiconductor device of claim 7 , wherein said third PN junction is punched through by regulating the doping concentration of said first doped region and said epitaxy semiconductor layer.

10. The semiconductor device of claim 1 , further comprising an isolation structure for defining active regions of said first and second transistors.

11. The semiconductor device of claim 10 , wherein said isolation structure comprises a first side that adjoins said semiconductor buried layer and said first epitaxy region, and a second side that adjoins said second epitaxy region.

12. The semiconductor device of claim 10 , wherein said isolation structure is selected from a trench and a doped diffusion region of said first conductivity type.

13. The semiconductor device of claim 12 , wherein said doped diffusion region extends to said semiconductor substrate from the surface of said epitaxy semiconductor layer.

14. The semiconductor device of claim 1 , further comprising:
a) a first electrode contacting with said second and third doped regions; and
b) a second electrode contacting with said semiconductor substrate.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yao Fei
• Wang Shijun
• Qin Bo

Classifications

• H01L29/747

  Electricity · mapped topic

• H01L29/7424 Primary

  Electricity · mapped topic

• H01L29/66386

  Electricity · mapped topic

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D18/80

  Bidirectional devices, e.g. triacs · CPC title