Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9679982-B2
Application number	US-201414162859-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively.

First claim

What is claimed is:

1. A semiconductor device comprising:
a device isolation pattern disposed in a substrate to define an active portion;
a pair of gate electrodes disposed in a pair of gate grooves crossing the active portion, respectively, wherein a top surface of a center portion of the active portion between the pair of gate grooves is lower than top surfaces of opposing edge portions of the active portion and wherein top surfaces of the gate electrodes are lower than the top surface of the center portion of the active portion;
a gate insulating layer disposed between each of the gate electrodes and an inner surface of each of the gate grooves;
gate capping patterns filling the gate grooves on the gate electrodes, respectively;
a contact pattern connected to the center portion of the active portion;
a wire pattern including a conductive wire extending in a first direction on the contact pattern; and
an insulating pattern disposed between the conductive wire and the device isolation pattern,
wherein a top surface of the insulating pattern directly contacts the conductive wire,
wherein the gate capping patterns comprise portions that extend outside the gate grooves to be connected to each other without an interface therebetween, and the portions of the gate capping patterns comprises a connected extending portion, and
wherein a sidewall of the contact pattern is in contact with the gate capping patterns.

2. The semiconductor device of claim 1 , wherein the connected extending portion of the gate capping patterns comprises one united body extension, and
wherein the one united body extension defines an opening exposing the center portion of the active portion, and the contact pattern is in the opening.

3. The semiconductor device of claim 2 , wherein the opening has a closed loop-shape in a plan view.

4. The semiconductor device of claim 2 , wherein concave regions are formed in the connected extending portion of the gate capping patterns on each of the gate electrodes, and
wherein the concave regions are laterally connected to the opening.

5. The semiconductor device of claim 4 , wherein a bottom surface of each of the concave regions is higher than a bottom surface of the opening.

6. The semiconductor device of claim 4 , further comprising:
insulating spacers disposed on both sidewalls of the wire pattern, respectively; and
an insulator disposed in each of the concave regions,
wherein the insulator is formed of the same material as the insulating spacers, and
wherein an interface exists between the insulator and an inner surface of the concave region.

7. The semiconductor device of claim 2 , wherein a width of the contact pattern is less than a width of the opening in a second direction perpendicular to the first direction.

8. The semiconductor device of claim 1 , wherein the contact pattern has both sidewalls aligned with both sidewalls of the conductive wire, respectively.

9. The semiconductor device of claim 1 , wherein a top surface of the device isolation pattern under the connected extending portion of the gate capping patterns is lower than the top surfaces of the edge portions of the active portion.

10. The semiconductor device of claim 1 , wherein a width of the connected extending portion of the gate capping patterns is less than a width of the gate capping pattern in the gate groove.

11. The semiconductor device of claim 1 , further comprising:
a first source/drain region in the center portion of the active portion;
a second source/drain region in one of the edge portions of the active portion; and
a data storage part electrically connected the second source/drain region.

12. The semiconductor device of claim 1 , wherein the gate capping patterns connect to each other to overlap a protruding portion of the device isolation pattern.

13. A semiconductor device comprising:
first and second gate electrodes in respective recessed portions of a substrate, the first and second gate electrodes extending in a first direction;
an isolation pattern disposed in the substrate to define an active portion, wherein a portion of the isolation pattern is between the first and second gate electrodes;
first and second gate capping patterns on the first and second gate electrodes, respectively, the first and second gate capping patterns extending continuously from a first sidewall of the isolation pattern to a second sidewall of the isolation pattern to connect to each other to overlap the portion of the isolation pattern that is between the first and second gate electrodes;
a contact pattern connected to a center portion of the active portion between the first and second gate electrodes; and
a conductive wire extending in a second direction that is perpendicular to the first direction on the contact pattern,
wherein both sidewalls of the contact pattern are aligned with both sidewalls of the conductive wire.

14. The semiconductor device of claim 13 , further comprising:
a third gate electrode in another recessed portion of the substrate; and
a third gate capping pattern on the third gate electrode,
wherein the substrate comprises a first protruding active portion that protrudes between the second and third gate electrodes such that a third sidewall of the first protruding active portion is adjacent the second gate electrode and the second gate capping pattern and a fourth sidewall of the first protruding active portion is adjacent the third gate electrode and the third gate capping pattern, and
wherein the substrate comprises a second protruding active portion that is spaced apart from the first protruding active portion and protrudes beyond the first protruding active portion.

15. The semiconductor device of claim 13 , further comprising a mask pattern on the isolation pattern,
wherein a sidewall of the mask pattern is aligned with a sidewall of the isolation pattern, and
wherein a top surface of the mask pattern is coplanar with top surfaces of the first and second gate capping patterns.

16. The semiconductor device of claim 13 , wherein a width of the conductive wire in the first direction is substantially the same as a width of the contact pattern in the first direction.

17. The semiconductor device of claim 1 , wherein the insulating pattern contacts a top surface of the device isolation pattern.

18. The semiconductor device of claim 1 , wherein the connected extending portion of the gate capping patterns comprises a first portion, which is between the contact pattern and one of the edge portions of the active portion and is disposed below the top surface of the insulating pattern, and a second portion, which is on a portion of the device isolation pattern disposed between the pair of gate electrodes and is disposed below the top surface of the insulating pattern, and
wherein the first portion of the connected extending portion has a first width in the first direction, the second portion of the connected extending portion has a second width in a second direction that is perpendicular to the first direction, and the first width and the second width are equal.

19. The semiconductor device of claim 1 , wherein the active portion comprises a first active portion, the pair of gate electrodes comprises a first pair of gate electrodes, the pair of gate grooves comprise a first pair of gate grooves, and the gate capping patterns comprise a first gate capping pattern that fills one of the first pair of gate grooves on one of the first pair of gate electrodes,
wherein the first gate capping pattern compr

Assignees

• Kim Daeik
• Kim Jiyoung
• Park Jemin
• Son Nakjin
• Hwang Yoosang
• Samsung Electronics Co Ltd

Inventors

• Kim Daeik
• Kim Jiyoung
• Park Jemin
• Son Nakjin
• Hwang Yoosang

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/7831

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/4236 Primary

  Electricity · mapped topic