Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors

Patent metadata

Field	Value
Publication number	US-9679960-B2
Application number	US-201615177640-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	May 15, 2012
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.

First claim

What is claimed is:

1. A method of manufacturing a capacitor, the method comprising:
forming a trench in a layer, the trench exposing a portion of a major surface of a substrate;
depositing a bottom electrode material on a bottom surface and sidewalls of the trench;
forming on the bottom electrode material and within the trench a dielectric material having edges proximate a major surface of the layer;
depositing over the dielectric material a top electrode material, the top electrode material filling the trench; and
removing a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.

2. The method of claim 1 , wherein after removing the portion of the bottom electrode material and the portion of the top electrode material, the edges of the dielectric material are substantially coplanar with the major surface of the layer.

3. The method of claim 1 , wherein removing the portion of the bottom electrode material and the portion of the top electrode material comprises an etching process, wherein the etching process is selective to the dielectric material.

4. The method of claim 1 , wherein depositing the bottom electrode material comprises conformally depositing the bottom electrode material on the bottom surface and sidewalls of the trench.

5. The method of claim 1 , wherein the bottom electrode material comprises a material selected from the group consisting essentially of TiN, TaN, W, WN, Ru, Ir, Pt, and combinations thereof.

6. The method of claim 1 , wherein removing the portion of the bottom electrode material and the portion of the top electrode material comprises an isotropic etch process.

7. The method of claim 1 , wherein removing the portion of the bottom electrode material and the portion of the top electrode material comprises simultaneously removing the portion of the bottom electrode material and the portion of the top electrode material.

8. A method of manufacturing a semiconductor device, the method comprising:
performing a first etch process to form a planar capacitor, the planar capacitor comprising a bottom electrode, a capacitor dielectric over the bottom electrode, and a top electrode over the capacitor dielectric, the capacitor dielectric comprising a first edge and a second edge opposite the first edge; and
performing a second etch process to remove portions of the bottom electrode and the top electrode proximate the first edge and the second edge of the capacitor dielectric.

9. The method of claim 8 , wherein after performing the second etch process, the first edge and the second edge of the capacitor dielectric extend beyond edges of the bottom electrode and the top electrode by about 5 to 300 Angstroms.

10. The method of claim 8 , wherein performing the second etch process further removes a portion of a top surface of the top electrode.

11. The method of claim 8 , wherein performing the first etch process damages the first edge and the second edge of the capacitor dielectric.

12. The method of claim 8 , further comprising coupling a conductive feature to the top electrode after performing the second etch process.

13. The method of claim 8 , wherein the bottom electrode comprises a first layer adjacent the capacitor dielectric and a second layer adjacent the first layer, wherein the first layer comprises a material selected from the group consisting essentially of TiN, TaN, W, WN, Ru, Ir, Pt, and combinations thereof, and wherein the second layer comprises a material selected from the group consisting essentially of Cu, Ti, Ta, W, Ru, WN, Ir, Pt, and combinations thereof.

14. The method of claim 13 , wherein performing the second etch process to remove portions of the bottom electrode and the top electrode comprises removing portions of the first layer but not the second layer of the bottom electrode.

15. A method of manufacturing a semiconductor device, the method comprising:
forming a capacitor, wherein forming the capacitor comprises forming a bottom electrode over a substrate, forming a capacitor dielectric over the bottom electrode, and forming a top electrode over the capacitor dielectric, the capacitor dielectric having a first end and a second end opposite the first end;
removing portions of the bottom electrode and the top electrode proximate the first end and the second end of the capacitor dielectric; and
coupling a conductive feature to the capacitor.

16. The method of claim 15 , wherein forming the capacitor further comprises:
etching a trench in the substrate, the substrate having a major surface;
forming a bottom electrode material on the major surface of the substrate and on a bottom surface and sidewalls of the trench;
forming a capacitor dielectric material on the bottom electrode material;
forming a top electrode material on the capacitor dielectric material; and
removing the bottom electrode material, the capacitor dielectric material, and the top electrode material from outside the trench, leaving the bottom electrode, the capacitor dielectric, and the top electrode within the trench, the first end and the second end of the capacitor dielectric being substantially coplanar with the major surface of the substrate after the removing step.

17. The method of claim 16 , wherein removing the bottom electrode material, the capacitor dielectric material, and the top electrode material from outside the trench comprises a chemical mechanical polishing process, and wherein the major surface of the substrate is exposed after the chemical mechanical polishing process.

18. The method of claim 16 , wherein coupling the conductive feature to the capacitor comprises:
forming a via over the top electrode; and
forming a conductive line over the via.

19. The method of claim 15 , wherein forming the capacitor further comprises:
forming a bottom electrode material on a major surface of the substrate;
forming a capacitor dielectric material on the bottom electrode material;
forming a top electrode material on the capacitor dielectric material;
forming a photoresist material on the top electrode material;
patterning the photoresist material; and
etching the bottom electrode material, the capacitor dielectric material, and the top electrode material using the patterned photoresist material as a mask to form the bottom electrode, the capacitor dielectric, and the top electrode, respectively.

20. The method of claim 19 , further comprising removing the photoresist material after the step of removing portions of the bottom electrode and the top electrode proximate the first end and the second end of the capacitor dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tu Kuo-Chi

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H01L28/60

  Electricity · mapped topic

• H01L28/40

  Electricity · mapped topic

• H01L28/65

  Electricity · mapped topic

• H01L21/32134

  Electricity · mapped topic