Optimized ESD clamp circuitry

Patent metadata

Field	Value
Publication number	US-9679891-B2
Application number	US-201414220293-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Mar 20, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

First claim

What is claimed is:

1. An apparatus comprising:
a first sensor circuit;
a second sensor circuit, wherein each of the first and second sensor circuits are configured to detect an electro-static discharge (ESD) event; and
first and second clamp transistors configured to be activated by the first and second sensor circuits, respectively, responsive to detection of the ESD event;
wherein a resistive-capacitive (RC) time constant of the first sensor circuit is greater than an RC time constant of the second sensor circuit;
wherein at least one of the first and second clamp transistors is coupled to well-biasing circuitry, wherein the well-biasing circuitry includes a pull-up transistor and a pull-down transistor coupled together and further coupled to a well of the clamp transistor, wherein the well-biasing circuitry is configured to bias a threshold voltage of the clamp transistor.

2. The apparatus as recited in claim 1 , wherein the first and second sensor circuits are implemented in a global power domain, and wherein the first and second clamp transistors are implemented in a gated power domain.

3. The apparatus as recited in claim 2 , further comprising first and second power switches coupled between the global power domain and the gated power domain, wherein the first and second sensor circuits are configured to cause activation of the first and second power switches, respectively, responsive to the ESD event.

4. The apparatus as recited in claim 1 , wherein the first sensor circuit is a first type of sensor circuit and the second sensor circuit is a second type of sensor circuit, wherein the circuit further comprises multiple instances of the second type of sensor circuit for each instance of the first type of sensor circuit.

5. The apparatus as recited in claim 1 , wherein the first sensor circuit includes a first pre-driver circuit coupled to a gate terminal of the first clamp transistor and wherein the second sensor circuit includes a second circuit coupled to a gate terminal of the second clamp transistor.

6. The apparatus as recited in claim 1 , wherein the first sensor circuit is configured to activate, responsive to detection of the ESD event, each of a first plurality of clamp transistors, the first plurality of clamp transistors including the first clamp transistor, and wherein the second sensor circuit is configured to, responsive to detection of the ESD event, activate each of a second plurality of clamp transistors, the second plurality of clamp transistors including the second clamp transistor.

7. The apparatus as recited in claim 1 , further comprising:
a first plurality of sensor circuits including the first sensor circuit;
a first plurality of clamp transistors including the first clamp transistor, wherein each of the first plurality of sensor circuits is configured to activate a corresponding unique one of the first plurality of clamp transistors;
a second plurality of sensor circuits including the second sensor circuit; and
a second plurality of clamp transistors including the second clamp transistor, wherein each of the second plurality of sensor circuits is configured to activate a corresponding unique one of the second plurality of clamp transistors.

8. The apparatus as recited in claim 1 , wherein the first and second sensor circuits and the first and second clamp transistors are implemented in a first power domain.

9. A method comprising:
first and second sensor circuits each detecting an electro-static discharge (ESD) event; and
the first and second sensor circuits activating first and second clamp transistors, respectively, responsive to detecting the ESD event, wherein a resistive-capacitive (RC) time constant of the first sensor circuit is greater than an RC time constant of the second sensor circuit;
wherein the method further comprises biasing a threshold voltage of at least one of the first and second clamp transistors using well-biasing circuitry having a pull-up transistor and a pull-down transistor coupled together and further coupled to a well of the at least one of the first and second clamp transistors.

10. The method as recited in claim 9 , further comprising:
the first and second sensor circuits detecting the ESD event in a global power domain; and
the first and second sensor circuits causing activation of first and second power switches coupled between the global power domain and a gated power domain, wherein the first and second clamp transistors are implemented in the gated power domain.

11. The method as recited in claim 9 , further comprising:
the first sensor circuit activating each of a first plurality of clamp transistors responsive to detecting the ESD event, the first plurality of clamp transistors including the first clamp transistor; and
the second sensor circuit activating each of a second plurality of clamp transistors responsive to detecting the ESD event, the second plurality of clamp transistors including the second clamp transistor.

12. The method as recited in claim 9 , further comprising, subsequent to activating the first and second clamp transistors, the second sensor circuit deactivating the second clamp transistor prior to the first sensor circuit deactivating the first clamp transistor.

13. An integrated circuit comprising:
a charged device model (CDM) sensor configured to detect an electro-static discharge (ESD) event, the CDM sensor circuit having a first resistive-capacitive (RC) time constant;
a first transistor coupled to the CDM sensor, wherein the CDM sensor is configured to cause activation of the first transistor responsive to detecting the ESD event;
a human body model (HBM) sensor, the HBM sensor circuit having a second RC time constant that is at least one order of magnitude greater than the first RC time constant; and
a second transistor coupled to the HBM sensor, wherein the HBM sensor is configured to cause activation of the second transistor responsive to detecting the ESD event;
wherein at least one of the first and second transistors is coupled to well-biasing circuitry, wherein the well-biasing circuitry includes a pull-up transistor and a pull-down transistor coupled together and further coupled to a well of the at least one of the first and second transistors, wherein the well-biasing circuitry is configured to bias a threshold voltage of the at least one of the first and second transistors.

14. The integrated circuit as recited in claim 13 , wherein responsive to detecting the ESD event, the CDM sensor is configured to activate the first transistor prior to the HBM sensor activating the second transistor, and wherein the HBM sensor is configured to deactivate the second transistor subsequent to the CDM sensor deactivating the first transistor.

15. The integrated circuit as recited in claim 13 , wherein the CDM and HBM sensors are implemented in a global power domain, and wherein the first and second transistors are implemented in a gated power domain.

16. The integrated circuit as recited in claim 15 , wherein responsive to detecting the ESD event, the CDM sensor is configured to cause activation of a first power switch and wherein the HBM sensor is configured to cause activation of a second power switch, wherein the first and second power switches are coupled between the global power domain and the gated power domain.

17. The integrated circuit as recited in claim 16 , further comprising a power control circuit configured to cause activation of the first and second power switches independent of activation of the first and second transistors.

18. The integr

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Fan Xiaofeng
• Joordens Geertjan

Classifications

• H02H3/22

  of short duration, e.g. lightning · CPC title

• H01L27/0285 Primary

  Electricity · mapped topic

• H02H3/20

  responsive to excess voltage · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title