Semiconductor constructions

Patent metadata

Field	Value
Publication number	US-9679852-B2
Application number	US-201414321466-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 1, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

First claim

We claim:

1. A construction, comprising:
a conductive line extending lengthwise in a first direction and having an upper surface extending along the first direction;
a plurality of conductive interconnects electrically coupled with the upper surface of the conductive line and spaced laterally from one another along the first direction by intervening regions over the conductive line; the conductive interconnects having first widths along the first direction in wide upper regions and having second widths along the first direction in narrow lower regions;
first air gap/spacer insulative structures within the intervening regions between the narrow lower regions of the conductive interconnects, the first air gap/spacer insulative structures comprising first dielectric spacers along sidewalls of the conductive interconnects, and comprising first regions of air gaps between the first dielectric spacers; and
second air gap/spacer insulative structures within the intervening regions between the wide upper regions of the conductive interconnects, the second air gap/spacer insulative structures comprising second dielectric spacers along sidewalls of the conductive interconnects, and comprising second regions the air gaps between the second dielectric spacers; within individual intervening regions, the second air gaps of the second air gap/spacer insulative structures merging with the first air gaps of the first air gap/spacer insulative structures with the second air gaps having a lateral width along the first direction that is greater than a lateral width of the first air gaps along the first direction.

2. The construction of claim 1 wherein the conductive line comprises a different composition than the conductive interconnects.

3. The construction of claim 2 wherein the conductive line comprises copper and the conductive interconnects comprise tungsten.

4. The construction of claim 1 wherein the first dielectric spacers comprise a different composition than the second dielectric spacers.

5. The construction of claim 4 wherein the first dielectric spacers comprise one or both of silicon nitride and silicon dioxide; and wherein the second dielectric spacers comprise one or more of aluminum oxide, hafnium oxide, silicon oxide, zirconium oxide and silicon nitride.

6. The construction of claim 4 wherein the first dielectric spacers are a single homogenous material; and wherein the second dielectric spacers are a laminate of two or more different materials.

7. The construction of claim 4 wherein the first dielectric spacers are wider than the second dielectric spacers.

Assignees

• Micron Technology Inc

Inventors

• Dutta Ashim
• Akhtar Mohd Kamran
• Trapp Shane J

Classifications

• H10W20/0886

  involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/483

  Interconnections over air gaps, e.g. air bridges · CPC title