Substrate and method of forming the same

Patent metadata

Field	Value
Publication number	US-9679841-B2
Application number	US-201414276763-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	May 13, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

First claim

What is claimed is:

1. A substrate prepared by a process comprising:
laminating a photoactive dielectric layer directly on a copper layer of a core material;
forming a plurality of trace patterns in the photoactive dielectric layer;
plating the plurality of trace patterns to form a plurality of traces embedded in the photoactive dielectric layer;
forming an insulating dielectric layer on the photoactive dielectric layer after plating the plurality of trace patterns, the insulating dielectric layer covering the plurality of traces and comprising a non-photoactive dielectric layer;
forming a via through the insulating dielectric layer and the photoactive dielectric layer;
forming additional routing patterns on the insulating dielectric layer;
removing the core material; and
applying a solder mask.

2. The product of the process of claim 1 , wherein each of the plurality of traces has a width of 5 μm and a gap of 5 μm between each of the plurality of traces.

3. The product of the process of claim 1 , wherein each of the plurality of traces has a width of 2 μm and a gap of 2 μm between each of the plurality of traces.

4. The product of the process of claim 1 , wherein the via is a skip via.

5. The product of the process of claim 1 , wherein the via is a padless skip via.

6. The product of the process of claim 1 , wherein the photoactive dielectric layer is less than 10 μm.

7. The product of the process of claim 1 , wherein the photoactive dielectric layer is approximately 5 μm.

8. The product of the process of claim 1 , wherein the insulating dielectric layer is approximately 15 μm.

9. The product of the process of claim 1 , wherein the via has a top portion smaller than a bottom portion.

10. A semiconductor structure comprising:
a coreless substrate, the coreless substrate comprises a permanent photoactive dielectric layer and an insulating dielectric layer on the permanent photoactive dielectric layer;
a plurality of traces embedded in the permanent photoactive dielectric layer, wherein the insulating dielectric layer covers the plurality of traces and comprises a different material than the photoactive dielectric layer;
a first via that extends through the insulating dielectric layer and the permanent photoimageable dielectric layer;
a second via, proximate to the first via, that extends through the insulating dielectric layer and the permanent photoimageable dielectric layer; and
a via trace embedded in a solder resist laminate layer on the insulating dielectric layer, the via trace configured to connect the first via and the second via.

11. The semiconductor structure of claim 10 , wherein each of the plurality of traces has a width of 5 μm and a gap of 5 μm between each of the plurality of traces.

12. The semiconductor structure of claim 10 , wherein each of the plurality of traces has a width of 2 μm and a gap of 2 μm between each of the plurality of traces.

13. The semiconductor structure of claim 10 , wherein the via is a skip via.

14. The semiconductor structure of claim 10 , wherein the via is a padless skip via.

15. The semiconductor structure of claim 10 , wherein the photoactive dielectric layer is less than 10 μm.

16. The semiconductor structure of claim 10 , wherein the photoactive dielectric layer is approximately 5 μm.

17. The semiconductor structure of claim 10 , wherein the insulating dielectric layer is approximately 15 μm.

18. The semiconductor structure of claim 10 , wherein the insulating dielectric layer is a non-photoactive dielectric layer.

19. A semiconductor structure, comprising:
a coreless substrate, the coreless substrate comprises a permanent photoactive dielectric layer and an insulating dielectric layer;
a plurality of traces embedded in the permanent photoactive dielectric layer, wherein the insulating dielectric layer covers the plurality of traces and comprises a different material than the photoactive dielectric layer;
first means for conducting, the first means for conducting extends through the insulating dielectric layer and the permanent photoimageable dielectric layer;
second means for conducting, proximate to the first means for conducting, that extends through the insulating dielectric layer and the permanent photoimageable dielectric layer; and
a via trace embedded in a solder resist laminate layer on the insulating dielectric layer, the via trace configured to connect the first means for conducting and the second means for conducting.

20. The semiconductor structure of claim 19 , wherein each of the plurality of traces has a width of 5 μm and a gap of 5 μbetween each of the plurality of traces.

21. The semiconductor structure of claim 19 , wherein each of the plurality of traces has a width of 2 μm and a gap of 2 μm between each of the plurality of traces.

Assignees

• Qualcomm Inc

Inventors

• Jomaa Houssam Wafic
• Bchir Omar James
• Kang Kuiwon
• Kim Chin-Kwan

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title