Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9679829-B2
Application number	US-201514809159-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Sep 25, 2012
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a via hole through a first surface of a substrate to penetrate at least a portion the substrate;
forming a metal layer partially filling the via hole, the metal layer including a body portion filling more than half of the via hole from a bottom of the via hole and an extended portion protruding from a top surface of the body portion along an upper sidewall of the via hole, the metal layer including a hole region defined by the top surface of the body portion and an inner sidewall of the extended portion at an upper region of the via hole, and the metal layer including copper;
forming an alloy layer on the metal layer and in the hole region to substantially fill the via hole, the alloy layer containing at least one metallic element that is different from that in the metal layer and not containing copper; and
polishing a second surface of the substrate opposite the first surface of the substrate to expose the metal layer.

2. The method of claim 1 , wherein forming of the metal layer comprises sequentially forming a barrier layer and a seed layer on a sidewall of the via hole.

3. The method of claim 2 , wherein the metal layer is formed to have a thickness on a sidewall of the via hole near a top surface of the via hole smaller than a thickness near a bottom surface of the via hole.

4. A method of fabricating a semiconductor device, comprising:
forming a via hole through a first surface of a substrate to penetrate at least a portion the substrate;
forming a metal layer in the via hole;
forming an alloy layer on the metal layer to substantially fill the via hole, the alloy layer containing at least one metallic element that is different from that in the metal layer; and
polishing a second surface of the substrate opposite the first surface of the substrate to expose the metal layer,
wherein forming of the metal layer comprises sequentially forming a barrier layer and a seed layer on a sidewall of the via hole,
wherein the metal layer is formed by an electroplating process using the seed layer, and
wherein forming of the metal layer further comprises interrupting an electric current applied to the seed layer to dissolve a portion of the metal layer formed on a sidewall of the via hole.

5. The method of claim 4 , wherein dissolving of the metal layer is performed to expose a portion of the seed layer, and wherein the alloy layer is formed by an electroplating process using the exposed seed layer.

6. The method of claim 4 , wherein dissolving of the metal layer is performed to dissolve a portion of the seed layer and expose the barrier layer.

7. The method of claim 1 , wherein the alloy layer is formed using a method different from that for forming the metal layer, and
wherein the method further comprises forming a conductive separation layer on a surface of the metal layer, before forming of the alloy layer.

8. The method of claim 1 , further comprising:
forming an integrated circuit on the first surface of the substrate;
forming a first interlayer insulating layer to cover the integrated circuit; and
forming an interconnection line on the first interlayer insulating layer in contact with the alloy layer,
wherein forming of the metal layer and the alloy layer is performed after forming the integrated circuit and the first interlayer insulating layer and before forming the interconnection line.

9. The method of claim 1 , further comprising forming an integrated circuit on a first surface of the substrate, and
wherein forming of the metal layer and the alloy layer is performed before forming the integrated circuit.

10. The method of claim 1 , further comprising:
forming an integrated circuit on the first surface of the substrate;
forming a first interlayer insulating layer to cover the integrated circuit;
forming an interconnection line on the first interlayer insulating layer in contact with the alloy layer; and
forming a second interlayer insulating layer on the interconnection line,
wherein forming of the metal layer and the alloy layer are performed after forming the second interlayer insulating layer.

11. A method of fabricating a semiconductor device, comprising:
forming an upper insulating layer on a first surface of a substrate having a second surface opposite to the first surface;
forming a via hole through the upper insulating layer on the first surface of the substrate to extend toward the second surface of the substrate;
forming a metal layer partially filling the via hole, the metal layer including a body portion filling more than half of the via hole from a bottom of the via hole and an extended portion protruding from a top surface of the body portion along an upper sidewall of the via hole, the metal layer including a hole region defined by the top surface of the body portion and an inner sidewall of the extended portion at an upper region of the via hole, and the metal including copper;
forming an alloy layer on the metal layer and in the hole region to substantially fill the via hole, the alloy layer containing at least one metallic element that is different from that in the metal layer and not containing copper;
performing a planarization process after forming the alloy layer to expose the upper insulating layer and the metal layer to form a through electrode in the via hole; and
polishing a second surface of the substrate to expose the through electrode.

12. The method of claim 11 , wherein further comprises forming a conductive separation layer on a surface of the metal layer, before forming of the alloy layer.

13. The method of claim 1 , further comprising: performing an annealing process to partially grow crystal grains in the metal layer after the alloy layer is formed.

14. The method of claim 13 , wherein a mean crystal grain size of the alloy layer is smaller than that of the metal layer after the annealing process is performed.

15. The method of claim 13 , wherein a mean crystal grain size of the extended portion is smaller than a mean crystal grain size of body portion after the annealing process is performed.

Assignees

• Moon Kwangjin
• Kang Sunghee
• Kim Taeseong
• Park Byung Lyul
• Park Yeun-Sang
• Bang Sukchul
• Samsung Electronics Co Ltd

Inventors

• Moon Kwangjin
• Kang Sunghee
• Kim Taeseong
• Park Byung Lyul
• Park Yeun-Sang
• Bang Sukchul

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title