Dual molded stack TSV package

Patent metadata

Field	Value
Publication number	US-9679801-B2
Application number	US-201514730171-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Jun 3, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

First claim

What is claimed is:

1. A package comprising:
a first redistribution layer (RDL) including a top side and a back side;
a second level die mounted on the top side of the first RDL;
wherein the back side of the first RDL is on a front surface of a first level die, and the front surface of the first level die includes a first plurality of first landing pads electrically connected to active devices in the first level die and a second plurality of second landing pads electrically connected a plurality of TSVs in the first level die; and
a second RDL including a top side and a back side, wherein the top side of the second RDL is on a back surface of the first level die.

2. The package of claim 1 , wherein the first level die comprises active devices, and the first level die is less than 50 μm thick.

3. The package of claim 2 , wherein the first level die comprises one or more interconnect layers between the active devices and the front surface of the first level die.

4. The package of claim 2 , further comprising a first level molding compound that encapsulates the first level die between the first RDL and the second RDL.

5. The package of claim 4 , further comprising a second level molding compound that encapsulates the second level die on the first RDL.

6. The package of claim 5 , further comprising a plurality of conductive pillars on the first RDL and extending through the second level molding compound.

7. The package of claim 6 , further comprising a second package bonded to the plurality of conductive pillars.

8. The package of claim 5 , further comprising a non-silicon component mounted on the first RDL, and the second level molding compound encapsulates the non-silicon component on the first RDL.

9. The package of claim 2 , further comprising a plurality of conductive bumps on the back side of the second RDL.

10. The package of claim 2 , wherein each TSV has a maximum width of 10 μm or less.

11. The package of claim 10 , wherein the first RDL is directly on the front surface of the first level die, the second RDL is directly on the back surface of the first level die, and the first RDL and the second RDL each have a maximum thickness of less than 30 μm.

12. A package comprising:
a first redistribution layer (RDL) including a top side and a back side;
a second level die mounted on the top side of the first (RDL);
wherein the back side of the first RDL is directly on a front surface of a first level die, the first level die comprises active devices and a plurality of through silicon vias (TSVs), and the first level die is less than 50 μm thick; and
a second RDL including a top side and a back side, wherein the top side of the second RDL is directly on a back surface of the first level die.

13. The package of claim 12 , wherein each TSV has a maximum width of 10 μm or less.

14. The package of claim 13 , wherein each TSV has an aspect ratio of less than 10:1 of first level die thickness: TSV maximum width.

15. The package of claim 12 , wherein the first RDL and the second RDL each have a maximum thickness of less than 30 μm.

16. The package of claim 12 , wherein the first level die comprises a density of at least 2,500 of the plurality of TSVs per mm 2 .

17. The package of claim 16 , wherein the first level die has a TSV keep out zone of less than 5 μm.

Assignees

• Apple Inc

Inventors

• Lai Kwan-Yu
• Zhai Jun
• Hu Kunzhong
• Carson Flynn P

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title