Anodized metal on carrier wafer

Patent metadata

Field	Value
Publication number	US-9679796-B2
Application number	US-201414525254-A
Country	US
Kind code	B2
Filing date	Oct 28, 2014
Priority date	Oct 28, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.

First claim

What is claimed is:

1. A method for processing a semiconductor wafer comprising:
bonding a semiconductor wafer to a handling wafer using an adhesive and release layer, wherein the handling wafer comprises an electrostatic layer covering a surface of a transparent handling material;
processing the semiconductor wafer while it is bonded to the handling wafer;
ablating the adhesive and release layer through the transparent handler; and
removing the semiconductor wafer from the handling wafer.

2. The method of claim 1 , wherein the electrostatic layer is removed prior to ablation.

3. The method of claim 2 , wherein the removal of the electrostatic layer is performed using an acid.

4. The method of claim 3 , wherein the acid has a pH ranging from about 2 to about 3.

5. The method of claim 1 , wherein the electrostatic layer is formed by depositing a metal layer on a surface of the transparent handling material, and then anodizing the metal layer.

6. The method of claim 5 , wherein anodizing the metal layer converts at least a portion of the metal layer into a metal oxide.

7. The method of claim 6 , wherein the metal is aluminum and the metal oxide is aluminum oxide.

8. A method for processing a semiconductor wafer comprising:
bonding a semiconductor wafer to a handling wafer, wherein the handling wafer comprises an electrostatic layer covering a surface of a transparent wafer; and
attaching an electrostatic chuck to the electrostatic layer covering the surface of the handling wafer.

9. The method of claim 8 , wherein the electrostatic layer is formed by depositing a metal layer on a surface of the transparent handling material, and then anodizing the metal layer.

10. The method of claim 9 , wherein anodizing the metal layer converts at least a portion of the metal layer into a metal oxide.

11. The method of claim 10 , wherein the metal layer is aluminum and the metal oxide is aluminum oxide.

12. The method of claim 9 , wherein the anodized metal layer is sealed or dyed.

13. A semiconductor structure comprising:
a transparent wafer;
an electrostatic layer located on a surface of the transparent wafer; and
a device wafer bonded to the transparent wafer;
wherein the electrostatic layer comprises a layer of metal, and a separate layer of an anodized component of the metal.

14. The structure of claim 13 , wherein the metal is aluminum and the electrostatic layer is capable of attaching to an electrostatic chuck.

15. The structure of claim 13 , wherein the electrostatic layer is porous.

16. The structure of claim 15 , wherein at least one pore in the porous electrostatic layer is filled with a non-conductive material.

17. The structure of claim 16 , wherein the non-conductive material is a chlorofluorocarbon.

18. The structure of claim 16 , wherein at least one pore in the porous electrostatic layer is filled with a conductive material.

19. The structure of claim 18 , wherein the conductive material comprises chromium, magnesium, or a combination thereof.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Arvin Charles L
• Cox Harry D
• Lubguban Jorge A
• Schuler Jennifer D

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title