Selective dopant junction for a group III-V semiconductor device

Patent metadata

Field	Value
Publication number	US-9679775-B2
Application number	US-201615211010-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Feb 27, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

First claim

What is claimed is:

1. A method of forming a dopant junction in a semiconductor device, the method comprising:
performing a surface modification treatment on an exposed surface of a semiconductor layer;
alloying a metal layer with a dopant material to form a semiconductor device junction;

wherein:
the semiconductor layer is composed of a Group III-V semiconductor material;
the criticality of the thickness of the dopant material is between 0.1 nm to 10 nm;
the surface modification treatment occurs in a low pressure vacuum chamber and wherein the surface modification treatment includes applying a stream of gaseous hydrogen to the exposed surface of the semiconductor layer at sufficient velocity for oxygen desorption to occur to form a water vapor, which thereby removes a plurality of surface oxides from the exposed surface of the semiconductor layer in order to provide an oxide-free surface for material adhesion, and wherein after the surface modification treatment, the semiconductor device remains in an oxygen free environment;
the dopant deposition is directly upon the semiconductor layer; and
each of the above processes occur at a low temperature.

2. The method of claim 1 , further comprising performing a low temperature anneal in an oxygen free environment in order to drive the dopant material into the semiconductor layer.

3. The method of claim 1 , wherein the low temperature at which each of the processes occur is a temperature less than or equal to 650° Celsius.

4. The method of claim 1 , wherein the surface modification treatment is performed at 10 −4 TORR to 10 −10 TORR.

5. The method of claim 1 , further comprising depositing the dopant material on the exposed surface of the semiconductor layer, wherein the dopant material is an n-type dopant material for a Group III-V semiconductor material and wherein depositing the dopant material is done by a selective epitaxial growth of the dopant material.

6. The method of claim 5 , wherein depositing the n-type dopant material is depositing the n-type dopant material composed of at least one of: Ge, SiGe, GeSn, Sn, SiC, SiGeC, GeC, and InP.

7. The method of claim 1 , wherein the low temperature anneal occurs in a hydrogen plasma.

8. The method of claim 1 , wherein the low temperature anneal forms a region in the semiconductor layer under the dopant material, and wherein the region is composed of the semiconductor material and a portion of the dopant material.

9. The method of claim 1 , wherein alloying the metal layer with the dopant material consumes the dopant layer.

10. The method of claim 1 , wherein after alloying the metal layer with the dopant material, the exposed surface of the semiconductor layer where the dopant material was deposited is oxide free.

Assignees

• IBM

Inventors

• Chan Kevin K
• Hopstaken Marinus J P
• Kim Young-Hee
• Kobayashi Masaharu
• Leobandung Effendi
• Neumayer Deborah A
• Park Dae-Gyu
• Rana Uzma
• Tai Tsong-Lin

Classifications

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P95/408

  of Group III-V semiconductors, e.g. to render them semi-insulating · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/171

  being group IV material · CPC title