Methods of operating a nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9679659-B2
Application number	US-201514859637-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Oct 20, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device which sequentially performs a plurality of erase loops to erase a memory block, the method comprising:
performing at least one of the erase loops;
performing a post-program operation on the memory block after the at least one erase loop is performed; and
performing the remaining erase loops by:
detecting a threshold voltage distribution of the memory block;
adjusting an erase voltage increment based on the detected threshold voltage distribution; and
performing at least one of the remaining erase loops using the adjusted erase voltage increment,

wherein the post-program operation is not performed when each of the remaining erase loops is performed, and
wherein detecting the threshold voltage distribution comprises detecting off cells that have a threshold voltage that is higher than an off cell voltage from among memory cells that are connected to an erase reference word line, wherein the erase reference word line is one of a plurality of word lines that are connected to the memory block.

2. The method of claim 1 , wherein adjusting the erase voltage increment comprises adjusting the erase voltage increment based on the number of off cells that are detected.

3. The method of claim 1 , wherein adjusting the erase voltage increment comprises adjusting a pulse width of an erase voltage based on the number of off cells that are detected.

4. A method of erasing a memory block of a nonvolatile memory device, the method comprising:
performing a first erase loop using a first erase scheme; and then
detecting a threshold voltage distribution of the memory block;
adjusting an erase voltage increment based on the detected threshold voltage distribution to provide an adjusted erase voltage increment; and
performing a second erase loop using a second erase scheme that is different from the first erase scheme, wherein the adjusted erase voltage increment is used in performing the second erase loop,
wherein the memory block includes a plurality of memory cells and a plurality of word lines are connected to the memory block, and
wherein detecting the threshold voltage distribution of the memory block comprises:
selecting a subset of the plurality of memory cells; and
detecting a number of the memory cells in the subset of the plurality of memory cells that have a threshold voltage that is higher than an off cell voltage.

5. The method of claim 4 , wherein the adjusted erase voltage increment is used to set voltages that are applied to a plurality of word lines that are connected to the memory block during the second erase loop.

6. The method of claim 4 , wherein adjusting the erase voltage increment based on the detected threshold voltage distribution to provide an adjusted erase voltage increment comprises adjusting the erase voltage increment based on the detected number of memory cells that have a threshold voltage that is higher than an off cell voltage.

7. The method of claim 4 , wherein the first erase scheme includes a post-program operation in which a plurality of program loops are performed, wherein each program loop includes a program step in which a program voltage is applied to a word line to program memory cells that are connected to the word line and a verification step where a program verification voltage is applied to verify program states of the memory cells, and wherein the second erase scheme does not include the post-program operation.

Assignees

• Shim Sunil
• Lim Joon-Sung
• Kang Jin-Kyu
• Kim Euido
• Yun Jang-Gn
• Samsung Electronics Co Ltd

Inventors

• Shim Sunil
• Lim Joon-Sung
• Kang Jin-Kyu
• Kim Euido
• Yun Jang-Gn

Classifications

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title