Electrically rewriteable nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8976597-B2
Application number	US-201113227050-A
Country	US
Kind code	B2
Filing date	Sep 7, 2011
Priority date	Feb 15, 2011
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising:
a memory cell array configured having a plurality of NAND cell units arranged therein, each NAND cell unit configured having a plurality of memory cells connected in series, each memory cell configured capable of storing an erase state in which data is erased from a memory cell and a write state in which data is written to a memory cell;
a plurality of word lines connected to the plurality of memory cel…

Assignees

• Shiino Yasuhiro
• Takahashi Eietsu
• Ueno Koki
• Toshiba Kk

Inventors

• Shiino Yasuhiro
• Takahashi Eietsu
• Ueno Koki

Classifications

• G11C16/16 Primary

  Physics · mapped topic

• G11C16/345

  Physics · mapped topic

• G11C16/3445

  Physics · mapped topic