Approach for context switching of lock-bit protected memory

Patent metadata

Field	Value
Publication number	US-9678897-B2
Application number	US-201213728813-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Dec 27, 2012
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.

First claim

What is claimed is:

1. A method for processing atomic operations for a plurality of threads in a multi-threaded architecture, the method comprising:
receiving a first request from a first thread in a first thread group to acquire access to a first memory location in a lock-protected shared memory;
determining whether a first address lock in a plurality of address locks is asserted, wherein the first address lock is associated with the first memory location;
if the first address lock is asserted, then
refusing the first request; or

if the first address lock is not asserted, then
asserting the first address lock;
asserting a first thread group lock in a plurality of thread group locks, wherein the first thread group lock is associated with the first thread group; and
granting the first request.

2. The method of claim 1 , wherein the first request is associated with an instruction to load a value from the first memory location.

3. The method of claim 1 , further comprising:
receiving a second request from the first thread to release access to the first memory location;
determining that the first thread group lock is asserted;
clearing the first address lock;
clearing the first thread group lock; and
granting the second request.

4. The method of claim 3 , wherein the second request is associated with an instruction to store a value into the first memory location.

5. The method of claim 1 , further comprising:
determining that at least one thread in the plurality of threads is subject to a context switch;
clearing each address lock in the plurality of address locks; and
clearing each thread group lock in the plurality of thread group locks.

6. The method of claim 5 , further comprising:
receiving a second request from the first thread to release access to the first memory location;
determining that the first thread group lock is cleared; and
refusing the second request.

7. The method of claim 5 , further comprising:
receiving a third request from a second thread in a second thread group to acquire access to the first memory location;
determining whether the first address lock is asserted;
if the first address lock is asserted, then
refusing the third request; or

if the first address lock is not asserted, then
asserting the first address lock;
asserting a second thread group lock in the plurality of thread group locks, wherein the second thread group lock is associated with the second thread group; and
granting the third request.

8. The method of claim 1 , wherein the first address lock is associated with the first memory location via a hash function.

9. The method of claim 1 , wherein the first address lock is included within a first bank associated with a plurality of banks of address locks.

10. A subsystem comprising:
a lock-protected shared memory; and
a streaming multiprocessor coupled to the lock-protected shared memory and configured to process atomic operations associated with the lock-protected shared memory by performing the steps of:
receiving a first request from a first thread in a first thread group to acquire access to a first memory location in a lock-protected shared memory;
determining that a first address lock in a plurality of address locks is not asserted, wherein the first address lock is associated with the first memory location;
asserting a first thread group lock associated with the first thread group; and
granting the first request.

11. The subsystem of claim 10 , wherein the first request is associated with an instruction to load a value from the first memory location.

12. The subsystem of claim 10 , wherein the streaming multiprocessor is further configured to perform the steps of:
receiving a second request from the first thread to release access to the first memory location;
determining that the first thread group lock is asserted;
clearing the first address lock;
clearing the first thread group lock; and
granting the second request.

13. The subsystem of claim 12 , wherein the second request is associated with an instruction to store a value into the first memory location.

14. The subsystem of claim 10 , wherein the streaming multiprocessor is further configured to perform the steps of:
determining that at least one thread in the plurality of threads is subject to a context switch; and
clearing each address lock in the plurality of address locks.

15. The subsystem of claim 14 , wherein the streaming multiprocessor is further configured to perform the steps of:
receiving a second request from the first thread to release access to the first memory location;
determining that the first thread group lock is cleared; and
refusing the second request.

16. The subsystem of claim 14 , wherein the streaming multiprocessor is further configured to perform the steps of:
receiving a third request from a second thread in a second thread group to acquire access to the first memory location;
determining whether the first address lock is asserted;
if the first address lock is asserted, then
refusing the third request; or

if the first address lock is not asserted, then
asserting the first address lock;
asserting a second thread group lock associated with the second thread group; and
granting the third request.

17. The subsystem of claim 10 , wherein the first address lock is associated with the first memory location via a hash function.

18. The subsystem of claim 10 , wherein the first address lock is included within a first bank associated with a plurality of banks of address locks.

19. A computing device configured to process atomic operations associated with a lock-protected shared memory comprising:
a shared memory; and
a streaming multiprocessor coupled to the shared memory and configured to
receive a first request from a first thread in a first thread group to acquire access to a first memory location in the shared memory;
determine that a first address lock associated with the first memory location is not asserted;
assert a first thread group lock associated with the first thread group; and
grant the first request.

20. The computing device of claim 19 , wherein the streaming multiprocessor is further configured to:
receive a second request from the first thread to release access to the first memory location;
clear the first thread group lock; and
grant the second request.

Assignees

• Nvidia Corp

Inventors

• Wang Nicholas
• Gadre Shirish
• Ohannessian Robert
• Shah Lacky V
• Brockmeyer Matthew
• Carlton Stewart Glenn

Classifications

• G06F12/1416 Primary

  by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title

• G06F12/1466 Primary

  Key-lock mechanism · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F16/1774

  Locking methods, e.g. locking methods for file systems allowing shared and concurrent access to files · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title