Peripheral test circuit of display array substrate and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-9678372-B2
Application number	US-201414383035-A
Country	US
Kind code	B2
Filing date	Jul 11, 2014
Priority date	May 21, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

The present disclosure relates to a peripheral test circuit of a display array substrate, and a liquid crystal display panel. The peripheral test circuit of a display array substrate includes: multiple groups of test signal lines, each group consisting of a first and a second test signal lines spaced from each other; a plurality of test pad leads, each being arranged in an interval formed between the first and the second test signal lines of a respective group, and connected with the first and the second test signal lines but not overlapped with the first and the second test signal lines of other groups; and a plurality of test pads, each being arranged on a respective test pad lead. According to the peripheral test circuit of the present disclosure, the problem existing in the current peripheral test circuit, i.e., a short circuit formed between the test pad lead and the test signal line due to electrostatic discharge caused by crossover between the test pad lead and the test signal line, can be overcome, thus reducing the injury risk of electrostatic discharge.

First claim

The invention claimed is:

1. A peripheral test circuit of a display array substrate, including:
multiple groups of test signal lines, each group of test signal lines consisting of a first test signal line and a second test signal line spaced from each other;
a plurality of test pad leads, each test pad lead being arranged in an interval formed between the first test signal line and the second test signal line of a respective group, and connected with the first test signal line and the second test signal line but not overlapped with the first test signal line and the second test signal line of other groups; and
a plurality of test pads, each test pad being arranged on a respective test pad lead,
wherein each test pad lead is connected with the first test signal line of the group associated with the test pad lead in a non-overlapping manner through a first passivation layer via hole and a second passivation layer via hole, and is connected with the second test signal line of the group associated with the test pad lead in a non-overlapping manner through a third passivation layer via hole and a fourth passivation layer via hole, and
wherein the first passivation layer via hole is a passivation layer via hole through which an ITO layer is connected with the first test signal line, the second passivation layer via hole is a passivation layer via hole through which the ITO layer is connected with the test pad lead, the third passivation layer via hole is a passivation layer via hole through which another ITO layer is connected with the second test signal line, and the fourth passivation layer via hole is a passivation layer via hole through which said another ITO layer is connected with the test pad lead.

2. The peripheral test circuit according to claim 1 , wherein the plurality of test pad leads are arranged in parallel but staggered from each other.

3. The peripheral test circuit according to claim 2 , wherein the first test signal line and the second test signal line of each group are respectively connected with a corresponding test pad lead along a direction perpendicular thereto.

4. A display array substrate, including a display area and a peripheral test circuit arranged around the display area,
said peripheral test circuit including:
multiple groups of a display array substrate test signal lines, each group of test signal lines consisting of a first test signal line and a second test signal line spaced from each other;
a plurality of test pad leads, each test pad lead being arranged in an interval formed between the first test signal line and the second test signal line of a respective group, and connected with the first test signal line and the second test signal line but not overlapped with the first test signal line and the second test signal line of other groups; and
a plurality of test pads, each test pad being arranged on a respective test pad lead,
wherein each test pad lead is connected with the first test signal line of the group associated with the test pad lead in a non-overlapping manner through a first passivation layer via hole and a second passivation layer via hole, and is connected with the second test signal line of the group associated with the test pad lead in a non-overlapping manner through a third passivation layer via hole and a fourth passivation layer via hole, and
wherein the first passivation layer via hole is a passivation layer via hole through which an ITO layer is connected with the first test signal line, the second passivation layer via hole is a passivation layer via hole through which the ITO layer is connected with the test pad lead, the third passivation layer via hole is a passivation layer via hole through which another ITO layer is connected with the second test signal line, and the fourth passivation layer via hole is a passivation layer via hole through which said another ITO layer is connected with the test pad lead.

5. The display array substrate according to claim 4 , wherein the plurality of test pad leads are arranged in parallel but staggered from each other.

6. The display array substrate according to claim 5 , wherein the first test signal line and the second test signal line of each group are respectively connected with a corresponding test pad lead along a direction perpendicular thereto.

7. A liquid crystal display panel, having a display array substrate including a display area and a peripheral test circuit arranged around the display area,
said peripheral test circuit including:
multiple groups of test signal lines, each group of test signal lines consisting of a first test signal line and a second test signal line spaced from each other;
a plurality of test pad leads, each test pad lead being arranged in an interval formed between the first test signal line and the second test signal line of a respective group, and connected with the first test signal line and the second test signal line but not overlapped with the first test signal line and the second test signal line of other groups; and
a plurality of test pads, each test pad being arranged on a respective test pad lead,
wherein each test pad lead is connected with the first test signal line of the group associated with the test pad lead in a non-overlapping manner through a first passivation layer via hole and a second passivation layer via hole, and is connected with the second test signal line of the group associated with the test pad lead in a non-overlapping manner through a third passivation layer via hole and a fourth passivation layer via hole, and
wherein the first passivation layer via hole is a passivation layer via hole through which an ITO layer is connected with the first test signal line, the second passivation layer via hole is a passivation layer via hole through which the ITO layer is connected with the test pad lead, the third passivation layer via hole is a passivation layer via hole through which another ITO layer is connected with the second test signal line, and the fourth passivation layer via hole is a passivation layer via hole through which said another ITO layer is connected with the test pad lead.

8. The liquid crystal display panel according to claim 7 , wherein the plurality of test pad leads are arranged in parallel but staggered from each other.

9. The liquid crystal display panel according to claim 8 , wherein the first test signal line and the second test signal line of each group are respectively connected with a corresponding test pad lead along a direction perpendicular thereto.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Fu Yanfeng

Classifications

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2635

  Testing light-emitting diodes, laser diodes or photodiodes · CPC title

• G02F1/1309 Primary

  Repairing; Testing · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F2001/136254

  Physics · mapped topic