TFT-LCD array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9366928-B2
Application number	US-201414557905-A
Country	US
Kind code	B2
Filing date	Dec 2, 2014
Priority date	May 7, 2010
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a display area comprising a gate line, a data line and a common electrode line, a pixel electrode and a first thin film transistor (TFT) formed in each sub-pixel area defined by the gate line and data line which are crossed with each other; and a test area located at the peripheral of the display area and comprising a first test one, a second test line, a testing electrode and a second TFT, and the common electrode line extending to the test area from the display area, wherein a part of the second test line constitutes a gate electrode of the second TFT; the source electrode of the second TFT is electrically connected with the first test line; a drain of the second TFT is electrically connected with the common electrode fine; and the common electrode line is connected with the testing electrode.

First claim

What is claimed is:

1. A thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising: a display area comprising a gate line, a data line and a common electrode one, a pixel electrode and a first thin film transistor (TFT) formed in each sub-pixel area defined by the gate line and data line which are crossed with each other; and a test area located at the peripheral of the display area and comprising a first test line, a second test one, a testing electrode and a second TFT, and the common electrode line extending to the test area from the display area, wherein a part of the second test line constitutes a gate electrode of the second TFT; the source electrode of the second TFT is electrically connected with the first test line; a drain of the second TFT is electrically connected with the common electrode line; and the common electrode line is connected with the testing electrode.

2. The TFT-LCD array substrate of claim 1 , wherein the first test line and the source electrode of the second TFT are formed integrally, or the first test line is connected with the source electrode of the second TFT through a via hole over the first test line, a via hole over the source electrode of the second TFT, and a first connecting electrode.

3. The TFT-LCD array substrate of claim 1 , wherein the first test line and the source and drain electrodes of the second TFT are formed on a same layer.

4. The TFT-LCD array substrate of claim 1 , wherein the first test line, the second test line, and the gate line are formed on a same layer.

5. The TFT-LCD array substrate of claim 1 , wherein the second test line, the common electrode line and the gate line are formed on a same layer, and the data line and the source and drain electrodes of the second TFT are formed on a same layer.

6. The TFT-LCD array substrate of claim 5 , wherein a testing via hole is formed over one end, which is adjacent to the second TFT, of the common electrode line, a third connecting via hole is formed over the drain electrode of the second TFT, the common electrode line is connected with the testing electrode through the testing via hole, and the drain electrode of the second TFT is connected with the testing electrode through the third connecting via hole.

7. The TFT-LCD array substrate of claim 1 , wherein the common electrode line, the data line, and the source and drain electrodes of the second TFT are formed on a same layer, the common electrode line comprises a plurality of common electrode strips and a plurality of second connecting electrodes with one common electrode strip formed in each sub-pixel area; among the sub-pixel areas in one row, the common electrode strips in two adjacent sub-pixel areas are connected with an intermediate second connecting electrode; and one end of the common electrode strip in the test area is connected with the drain electrode of the second TFT.

8. The TFT-LCD array substrate of claim 7 , wherein the common electrode strip adjacent to the second TFT and the drain electrode of the second TFT are formed integrally.

9. The TFT-LCD array substrate of claim 7 , wherein a fourth connecting via hole is formed over each end of each common electrode strip in the display area, and in the sub-pixel areas in one row, the common electrode strips in two adjacent sub-pixels are connected with each other through the fourth connecting via holes.

10. The TFT-LCD array substrate of claim 7 , wherein the common electrode line and the data line cross with each other, and the second connecting electrodes are provided at intersections between the common electrode line and the data line.

11. The TFT-LCD array substrate of claim 7 , wherein the common electrode strips are located in a same layer as the data line and not connected with the data line, and the second connecting electrodes are located in a different layer from the common electrode strips and cross over the data line so as to connect common electrode strips in adjacent sub-pixel areas.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Zhang Mi

Classifications

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/124

  Electricity · mapped topic