Electronic device and semiconductor package with thermally conductive via

Patent metadata

Field	Value
Publication number	US-9674940-B2
Application number	US-201514826207-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Aug 14, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

An electronic device and semiconductor package include a printed circuit board and a semiconductor device mounted thereon. The printed circuit board includes one or more thermally conductive vias for dissipating heat.

First claim

What is claimed is:

1. A semiconductor package comprising:
a printed circuit board; and
a semiconductor device mounted on the printed circuit board,
wherein the printed circuit board comprises:
at least a first power or ground pattern layer formed in the printed circuit board;
at least a first power or ground pad vertically aligned with the first power or ground pattern layer, and formed on a bottom surface of the printed circuit board;
at least a first electrically conductive via vertically aligned with the first power or ground pad, and that extends from the first power or ground pattern layer to the bottom surface of the printed circuit board to be connected to the first power or ground pad; and
at least a first thermally conductive via vertically aligned with the first electrically conductive via, and that extends from the first power or ground pattern layer to a top surface of the printed circuit board to be exposed to the outside of the printed circuit board,
wherein the first thermally conductive via, first electrically conductive via, first power or ground pad, and first power or ground pattern layer form a stack that is disposed in a region overlapping the semiconductor device when seen in a plan view,
wherein the first electrically conductive via is electrically and thermally connected to a plurality of thermally conductive vias that include the first thermally conductive via, which plurality of first thermally conductive vias terminate at the semiconductor device, and

wherein the at least the first power or ground pad is exposed through a protection layer at a bottom of the printed circuit board.

2. The semiconductor package of claim 1 , further comprising either an adhesive layer or an underfill layer, disposed between the printed circuit board and the semiconductor device,
wherein a top surface of the first thermally conductive via contacts the adhesive layer or the underfill layer.

3. The semiconductor package of claim 1 , wherein:
the semiconductor package is part of a memory card.

4. The semiconductor package of claim 1 , wherein a material of the first thermally conductive via is different from a material of the first electrically conductive via.

5. The semiconductor package of claim 1 , wherein a thermal conductivity of the first thermally conductive via is greater than a thermal conductivity of prepreg layers or a protection layer of the printed circuit board through which the first thermally conductive via passes.

6. The semiconductor package of claim 1 , wherein the printed circuit board comprises at least a first signal pattern layer formed thereinside, and the first thermally conductive via is electrically insulated from the first signal pattern layer.

7. The semiconductor package of claim 6 , wherein:
the semiconductor device includes a stack of semiconductor chips mounted on the printed circuit board.

8. The semiconductor package of claim 1 , wherein a top surface of the first thermally conductive via is disposed at a same level as the top surface of the printed circuit board.

9. The semiconductor package of claim 1 , wherein the semiconductor device is a first semiconductor chip, the semiconductor package further comprising:
a second semiconductor chip; and
an intermediate layer formed between a bottom of the first semiconductor chip and a top of the printed circuit board,
wherein the first semiconductor chip is adjacent to the printed circuit board,
wherein the first power or ground pad of the printed circuit board includes:
a first ground pad electrically connected to circuitry of the first semiconductor chip and for providing ground voltage to the first semiconductor chip, and a first power pad electrically connected to circuitry of the first semiconductor chip for providing power voltage to the first semiconductor chip,
wherein the printed circuit board further includes at least a first insulating layer contacting the intermediate layer, and
wherein the first thermally conductive via passes through the first insulating layer, extending between the intermediate layer and one of the first ground pad and the first power pad, electrically and thermally connected to one of the first ground pad and the first power pad, and contacting the intermediate layer.

10. The semiconductor package of claim 9 , wherein the first insulating layer is one of an underfill layer contacting the printed circuit board and the first semiconductor chip, or an adhesive layer contacting the printed circuit board and the first semiconductor chip.

11. The semiconductor package of claim 9 , wherein the first insulating layer is a prepreg layer disposed on a core layer of the printed circuit board.

12. The semiconductor package of claim 9 , wherein the first thermally conductive via is formed of a material different from the first insulating layer, and has a thermal conductivity greater than that of the first insulating layer.

13. The semiconductor package of claim 9 , wherein the first thermally conductive via extends to a surface of the printed circuit board and is positioned to receive heat from the first semiconductor chip and dissipate the heat toward a bottom of the printed circuit board.

14. The semiconductor package of claim 9 , wherein the first semiconductor chip includes a plurality of semiconductor chips.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Eung-Chang
• Han Seok-Jae

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title