System and method for reducing false preamble detection in a communication receiver

Patent metadata

Field	Value
Publication number	US-9673962-B1
Application number	US-201615045826-A
Country	US
Kind code	B1
Filing date	Feb 17, 2016
Priority date	Feb 17, 2016
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

First claim

The invention claimed is:

1. An apparatus comprising:
a signal detection circuit that includes a counter circuit configured to determine a count reached between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval;
a clock circuit that produces clock signal pulses in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval;
phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and
a pattern matching circuit configured to match a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

2. The apparatus of claim 1 further including:
a logic circuit configured to power up in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval.

3. The apparatus of claim 1 further including:
a logic circuit configured to power up in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval; and
a serializer/deserializer (SerDes) circuit operatively coupled between the clock circuit and the logic circuit.

4. The apparatus of claim 1 further including:
a processor circuit configured to power up in response to the provided indication indicating successive detected edge signals are separated from each other by at least the prescribed time interval; and
a serializer/deserializer (SerDes) circuit operatively coupled between the clock circuit and the processor circuit;
wherein the processor circuit is configured to provide a clearing interrupt in response to failure to receive a sync signal following the pattern matching circuit detecting of a packet preamble.

5. The apparatus of claim 1 ,
wherein the signal detection circuit provides a reset signal having a first value to indicate an occurrence of successive detected edge signals that are separated from each other by less than the prescribed time interval; and
wherein the signal detection circuit provides the reset signal having a second value to indicate an occurrence of successive detected edge signals that are separated from each other by at least the prescribed time interval.

6. The apparatus of claim 1 ,
wherein the signal detection circuit further includes a register to hold the count value reached between two successive detected edge signals.

7. The apparatus of claim 1 ,
wherein the signal detection circuit further includes a comparator configured to compare the count value reached between two successive detected edge signals with at least one threshold value and to provide the indication based at least in part upon the comparison.

8. The apparatus of claim 1 ,
wherein the signal detection circuit further includes:
a register to hold the count value reached between two successive detected edge signals; and
a comparator configured to compare the count value reached between two successive detected edge signals with at least one threshold value and to provide the indication based at least in part upon the comparison.

9. The apparatus of claim 1 ,
wherein the signal detection circuit further includes a comparator configured to compare the count value reached between two successive detected edge signals with at least one threshold value determined based at least in part upon a multiplier value (M) and to provide the indication based at least in part upon the comparison.

10. The apparatus of claim 1 ,
wherein the signal detection circuit further includes a comparator configured to compare the count value reached between two successive detected edge signals with at least one threshold value determined based at least in part upon a combination of a multiplier value (M) and an offset value and to provide the indication based at least in part upon the comparison.

11. The apparatus of claim 1 ,
wherein the signal detection circuit further includes:
a register to hold the count value reached between two successive detected edge signals;
a comparator configured to compare the count value reached between two successive detected edge signals with at least one threshold value and to provide the indication based at least in part upon the comparison; and
a window comparator configured to compare the count value reached between two successive detected edge signals with count range determined based at least in part at least in part upon a combination of a multiplier value (M) minus an offset value (M−offset) and the multiplier value (M) plus the offset value (M+offset) and to provide the indication based at least in part upon the comparison.

12. The apparatus of claim 1 ,
wherein the pattern matching circuit includes a register configured to hold a sequence of detected edge signals and a comparator configured to compare the sequence of detected edge signals with a prescribed packet preamble sequence.

13. The apparatus of claim 1 ,
wherein the clock circuit includes a cyclic counter.

14. The apparatus of claim 1 ,
wherein the clock circuit includes a cyclic counter configured to produce a clock signal pulse in response to the cyclic counter reaching a prescribed count.

15. The apparatus of claim 1 ,
wherein the phase matching circuitry includes:
a phase locked loop filter (PLL) coupled to receive a phase signal and to produce a PLL signal; and
a phase detector coupled to receive the edge detection signals, the clock signal pulses and the PLL signal and to produce the phase signal.

16. The apparatus of claim 1 ,
wherein the phase matching circuitry includes:
a phase locked loop (PLL) filter coupled to receive a phase signal and to produce a PLL signal;
a phase detector coupled to receive the edge detection signals, the clock signal pulses and the PLL signal and to produce the phase signal; and
a data rate correction and fractional rate support circuit coupled to receive the phase signal and the clock signal pulses and to produce a fractional data rate correction signal.

17. The apparatus of claim 1 further including:
an edge detector configured to detect the edge signals.

18. A method to detect a data packet comprising:
determining whether successive detected edge signals are separated from each other by at least a prescribed time interval;
producing clock signal pulses in response to a determination that a succession of detected edge signals each is separated from a previous edge signal of the succession by at least the prescribed time interval;
phase matching the produced clock signal pulses with the detected edge signals; and
matching a sequence of detected edge signals aligned to the produced clock signal pulses to detect the data packet.

19. The method of claim 18 further including:
powering up a logic circuit in response to the provided a determination that successive detected edge signals are separated from each other by at least the prescribed time interval.

20. The method of claim 18 further including:
wherein determining includes comparing a count value reached by a counter between two successive detected edge signals with at least one threshold value.

Assignees

• Analog Devices Global

Inventors

• Khan Muhammad Kalimuddin
• Mulvaney Kenneth J
• Quinlan Philip P E
• O'Mahony Shane

Classifications

• H04B17/29 Primary

  Performance testing · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/046

  using a dotting sequence · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title