Apparatuses, methods, and systems for jitter equalization and phase error detection

Patent metadata

Field	Value
Publication number	US-2016006544-A1
Application number	US-201414324062-A
Country	US
Kind code	A1
Filing date	Jul 3, 2014
Priority date	Jul 3, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

First claim

1 . A circuit comprising:
a first transmission path to pass a first signal, the first transmission path including one or more circuit blocks to receive a supply voltage and to process the first signal; a second transmission path to pass a second signal, the second transmission path including one or more circuit blocks to receive the supply voltage and to process the second signal; a jitter equalizer coupled with the first transmission path to introduce a delay to the first signal to provide an alignment between the first and second signals, wherein an amount of the delay is based on a value of the supply voltage; an error detector to measure a phase error between the first and second signals; and a training controller to adjust a delay setting of the jitter equalizer based on the measured phase error to obtain a calibrated delay setting; and a supply modulator to modulate the supply voltage by a modulation frequency during a training process of the circuit.

2 . The circuit of claim 1 , wherein the first signal is a clock signal and the second signal is a data signal.

3 . (canceled)

4 . (canceled)

5 . The circuit of claim 1 , wherein the modulation frequency is a first modulation frequency, wherein the calibrated delay setting is associated with the first modulation frequency, wherein the supply modulator is further to modulate the supply voltage at a second modulation frequency, and wherein the training controller is to obtain a second calibrated delay setting associated with the second modulation frequency.

6 . The circuit of claim 1 , wherein the training controller is to re-initiate the training process if a temperature associated with the circuit exceeds a respective threshold.

7 . The circuit of claim 1 , wherein the circuit is to provide a pre-determined data pattern for the data signal during the training process.

8 . The circuit of claim 1 , wherein the error detector is to:
perform an xor operation between the first and second signals to generate an xor signal; and determine a phase error between the first and second signals based on a mark/space ratio of the xor signal.

9 . The circuit of claim 8 , wherein the error detector is to determine the phase error based on the mark/space ratio of the xor signal by being configured to:
perform a logic and operation between the xor signal and an uncorrelated clock signal to generate a first count signal; perform a logic and operation between an xorb signal and the uncorrelated clock signal to generate a second count signal, the xorb signal being an inverted version of the xor signal; and determine the phase error between the first and second signals based on a difference between a first number of transitions in the first count signal and a second number of transitions in the second count signal.

10 . The circuit of claim 1 , wherein the value of the supply voltage is a voltage level of the supply voltage.

11 . A circuit comprising:
a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; and a phase error detector coupled to the first and second input terminals, the phase error detector to:
perform an XOR operation between the first and second input signals to generate an xor signal; and
determine a phase error between the first and second input signals based on a mark/space ratio of the xor signal by being configured to:
perform a logic AND operation between the xor signal and a clock signal to generate a first count signal;
perform a logic AND operation between the xor signal and the clock signal to generate a second count signal, the xorb signal being an inverted version of the xor signal; and
determine the phase error between the first and second input signals based on a difference between a first number of transitions in the first count signal and a second number of transitions in the second count signal over a same time period.

12 . (canceled)

13 . The circuit of claim 11 , wherein the clock signal is uncorrelated with the first or second input signals.

14 . The circuit of claim 11 , wherein the phase error detector is to generate an error code that corresponds to the determined phase error, and wherein the circuit further comprises a training controller coupled to the phase error detector, the training controller to adjust a delay of the first or second input signal based on the error code.

15 . The circuit of claim 11 , wherein the phase error detector is to generate an error code that corresponds to the determined phase error responsive to a determination that a difference between the first number of transitions and the second number of transitions is equal to or greater than a threshold.

16 . The circuit of claim 11 , wherein the phase error detector is further to:
count the first number of transitions and the second number of transitions for a pre-determined time period; and generate an error code to indicate a sense and a magnitude of the phase error.

17 . The circuit of claim 11 , wherein the phase error detector is to:
determine that that the first number of transitions or the second number of transitions is equal to or greater than a threshold; and generate an error code to indicate a sense and magnitude of the phase error responsive to the determination.

18 . A system, comprising:
a touchscreen display; a processor coupled to the touchscreen display; a power supply to provide a supply voltage; and a communication circuit coupled to the processor and to the power supply, the communication circuit including:
a supply modulator to modulate the supply voltage at a modulation frequency during a training process of the communication circuit;
a data path to pass a data signal, the data path including one or more circuit blocks to process the data signal;
a clock path to pass a clock signal, the clock path including one or more circuit blocks to process the clock signal;
a jitter equalizer coupled with the data path or the clock path to provide a delay to the respective data signal or clock signal;
an error detector to measure a phase error between the data signal and the clock signal; and
a training controller to, while the supply voltage is modulated at the modulation frequency, adjust the delay provided by the jitter equalizer based on the measured phase error.

19 . The system of claim 18 , wherein the modulation frequency is a first modulation frequency, wherein the training controller is further to, while the supply voltage is modulated at a second modulation frequency, adjust the delay provided by the jitter equalizer based on the measured phase error.

20 . The system of claim 18 , wherein the delay provided by the jitter equalizer varies with a voltage level of the supply voltage.

21 . The system of claim 18 , wherein the delay provided by the jitter equalizer varies with a frequency of a jitter component of the supply voltage.

22 . A method, comprising:
performing a logic XOR operation between first and second input signals to generate an xor signal; performing a logic AND operation between the xor signal and a clock signal to generate a first count signal; performing a logic AND operation between an xorb signal and the clock signal to generate a second count signal, the xorb signal being an inverted version of the xor signal; counting a number of rising edges in the first count signal for a time period to obtain a first counter value; counting a number of rising edges in the

Assignees

• Intel Corp

Inventors

• Cowley Nicholas P
• Kan Chi Man
• Saraswat Ruchir

Classifications

• H03K2005/00019

  Variable delay · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H04L1/205 Primary

  jitter monitoring · CPC title

• H03L7/097

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title

• H04B3/146

  using phase-frequency equalisers · CPC title