Calibration for echo cancellation in a full duplex communication system

Patent metadata

Field	Value
Publication number	US-9673959-B2
Application number	US-201414440589-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Sep 12, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

First claim

What is claimed is:

1. A device for full duplex communication over a channel, the device comprising:
a driver circuit and a replica driver circuit, an input of the driver circuit coupled to an input of the replica driver circuit and an output of the driver circuit coupled to an output of the replica driver circuit and further coupled to a channel, the driver circuit configured to produce an output data signal for transmission to the channel;
an echo cancellation circuit coupled to the replica driver circuit and the channel, the echo cancellation circuit configured to receive an input data signal from the channel, an echo of the output data signal, and a signal generated by the source replica driver circuit configured to cancel the echo; and
a calibration circuit coupled to receive an output of the echo cancellation circuit and to adjust the replica driver circuit; wherein during a calibration mode, the calibration module is configured to:
couple a local clock signal to the driver circuit and replica driver circuit, the driver circuit generating a reference signal from the local clock signal, the replica driver circuit generating a calibration signal from the local clock signal, and the echo cancellation circuit generating a difference signal between the reference signal and the calibration signal;
for multiple iterations, adjust the replica driver circuit to enable the reference signal and the calibration signal to cancel and record the corresponding values of the replica driver circuit adjustment; and
calibrate the replica driver circuit based on the recorded values of the replica driver circuit adjustment.

2. The device of claim 1 herein the calibration circuit adjusts the replica driver circuit based on whether the difference signal is above or below a reference voltage.

3. The device of claim 2 wherein the reference voltage is zero volts.

4. The device of claim 1 wherein the calibration circuit adjusts the replica driver circuit based on whether the difference signal is within a threshold range of a reference voltage.

5. The device of claim 1 wherein the calibration circuit adjusts the replica driver circuit to sweep the calibration signal to be alternately greater than and less than the reference signal, and determines whether the reference signal and the calibration signal cancel based on when the calibration signal toggles between being greater than and less than the reference signal.

6. The device of claim 1 wherein the replica driver circuit is calibrated based on an average of the recorded values.

7. The device of claim 1 wherein the calibration circuit further determines a calibration timing reference from the local clock signal, and determines whether the reference signal and the calibration signal cancel during time periods defined by the calibration timing reference.

8. The device of claim 1 wherein the calibration circuit further determines a mask period from the local clock signal, and determines whether the reference signal and the calibration signal cancel during the mask period.

9. The device of claim 8 wherein the local clock signal is constant during the mask period, and the calibration circuit determines whether the reference signal and the calibration signal cancel based on counting ones or zeroes during the mask period.

10. The device of claim 1 wherein the calibration circuit adjusts the replica driver circuit based on a phase of the difference signal.

11. The device of claim 1 wherein the device is a source device, no input data signal is received during the calibration mode, and timing of the output data signal is based on a clock generated by the source device.

12. The device of claim 1 wherein the device is a sink device, a remote clock signal is received as the input data signal during the calibration mode, and timing of the output data signal is based on the remote clock signal.

13. The device of claim 12 wherein the calibration circuit further generates a DC offset configured to cancel an offset added by the remote clock signal.

14. The device of claim 12 wherein the calibration circuit adjusts the replica driver circuit based on a phase of the difference signal.

15. The device of claim 12 wherein the local clock signal is phase shifted relative to the remote clock signal, and the calibration circuit adjusts the replica driver circuit based on a phase difference between the difference signal and the reference signal.

16. The device of claim 12 wherein the calibration circuit further determines a calibration timing reference from the remote clock signal, and determines whether the reference signal and calibration signal cancel during time periods defined by the calibration timing reference.

Assignees

• Silicon Image Inc
• Lattice Semiconductor Corp

Inventors

• Zhou Kai
• Tahk Shinje
• Lei Kai
• Wu Qiming
• Ahn Gijung
• Kim Min-Kyu
• Song Fei
• Luo Kexin

Classifications

• H04L5/1461 Primary

  Suppression of signals in the return path, i.e. bidirectional control circuits · CPC title

• H04B1/525

  with means for reducing leakage of transmitter signal into the receiver · CPC title

• H04M9/082

  using echo cancellers (echo cancellers per se H04B3/23) · CPC title

• H04L25/061

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04B3/232 Primary

  using phase shift, phase roll or frequency offset correction · CPC title