Image sensor isolation region and method of forming the same

Patent metadata

Field	Value
Publication number	US-9673244-B2
Application number	US-201213415546-A
Country	US
Kind code	B2
Filing date	Mar 8, 2012
Priority date	Mar 8, 2012
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.

First claim

What is claimed is:

1. A structure comprising:
a semiconductor substrate;
a photo element in the semiconductor substrate; and
an isolation region in the semiconductor substrate proximate the photo element, the isolation region comprising a dielectric material and an epitaxial region, the epitaxial region being disposed between the semiconductor substrate and the dielectric material, wherein the epitaxial region comprises a material that is lattice mismatched to a substrate material of the semiconductor substrate.

2. A structure comprising:
a semiconductor substrate;
a photo element in the semiconductor substrate; and
an isolation region in the semiconductor substrate proximate the photo element, the isolation region comprising a dielectric material and an epitaxial region, the epitaxial region being disposed between the semiconductor substrate and the dielectric material, the epitaxial region comprising a doped sub-region and an un-doped sub-region, wherein the un-doped sub-region is disposed adjacent a semiconductor sidewall of the semiconductor substrate and between the semiconductor substrate and the doped sub-region, the doped sub-region being disposed adjacent the un-doped sub-region and between the un-doped sub-region and the dielectric material.

3. The structure of claim 2 , wherein the doped sub-region comprises p-type doped silicon germanium, and the un-doped region comprises silicon germanium, and wherein the semiconductor substrate comprises silicon.

4. The structure of claim 1 , wherein the epitaxial region induces a stress in the semiconductor substrate.

5. The structure of claim 1 , wherein the epitaxial region is along surfaces of a trench in the semiconductor substrate.

6. A structure comprising:
a photo diode in a substrate;
an epitaxial layer on a surface of a trench in the substrate, the trench being proximate the photo diode, wherein the epitaxial layer comprises a material that is lattice mismatched to the substrate; and
an isolation material on the epitaxial layer, the epitaxial layer being disposed between the isolation material and the substrate.

7. The structure of claim 6 , wherein the epitaxial layer comprises a first sub-layer and a second sub-layer, the first sub-layer being proximate to the substrate, and the second sub-layer being distal from the substrate, a dopant concentration of the second sub-layer being greater than a dopant concentration of the first sub-layer.

8. The structure of claim 6 , wherein the epitaxial layer comprises silicon germanium and a p-type dopant, a concentration of the p-type dopant increasing in a direction from the surface of the trench toward a region distal from the surface, and wherein the substrate comprises silicon.

9. The structure of claim 6 , wherein the epitaxial layer induces a stress in the substrate.

10. A structure comprising:
a semiconductor substrate;
a photo element comprising a p-n junction and extending from a first side of the semiconductor substrate into the semiconductor substrate;
a p-doped well adjacent to the p-n junction and extending from the first side of the semiconductor substrate into the semiconductor substrate; and
an isolation structure in the p-doped well, the isolation structure comprising an epitaxial layer on a sidewall surface of a trench and an isolation material on the epitaxial layer, at least a first portion of the epitaxial layer being p-doped.

11. The structure of claim 10 , wherein the first portion of the epitaxial layer is distal from the sidewall surface of the trench, a second portion of the epitaxial layer being disposed between the first portion of the epitaxial layer and the sidewall surface, the second portion not being doped.

12. The structure of claim 10 , wherein the epitaxial layer comprises a crystalline material with lattice spacing different from a lattice spacing of a crystalline material of the semiconductor substrate.

13. The structure of claim 10 , wherein the epitaxial layer induces a stress in the semiconductor substrate.

14. The structure of claim 10 , wherein the semiconductor substrate comprises silicon, and the epitaxial layer comprises silicon germanium.

15. The structure of claim 10 further comprising:
at least one metallization dielectric layer comprising a metallization pattern on the first side of the semiconductor substrate; and
a lens and a filter on a second side of the semiconductor substrate, the second side being opposite the first side.

16. The structure of claim 1 further comprising:
at least one metallization dielectric layer comprising a metallization pattern on a first side of the semiconductor substrate; and
a lens and a filter on a second side of the semiconductor substrate, the second side being opposite the first side.

17. The structure of claim 6 further comprising:
at least one metallization dielectric layer comprising a metallization pattern on a first side of the substrate; and
a lens and a filter on a second side of the substrate, the second side being opposite the first side.

18. The structure of claim 1 further comprising a p-well disposed in the semiconductor substrate, the isolation region being disposed in the p-well, and the photo element being proximate the p-well and not disposed in the p-well.

19. The structure of claim 2 further comprising a p-well disposed in the semiconductor substrate, the isolation region being disposed in the p-well, and the photo element being proximate the p-well and not disposed in the p-well.

20. The structure of claim 6 further comprising a p-well disposed in the substrate, the trench being disposed in the p-well, and the photo diode being proximate the p-well and not disposed in the p-well.

Assignees

• Jangjian Shiu-Ko
• Hong min hao
• Chen Kei-Wei
• Wu Szu-An
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jangjian Shiu-Ko
• Hong min hao
• Chen Kei-Wei
• Wu Szu-An

Classifications

• H01L27/1463 Primary

  Electricity · mapped topic

• H01L27/1464

  Electricity · mapped topic

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/807 Primary

  Pixel isolation structures · CPC title