Efficient fabrication of BiCMOS devices

Patent metadata

Field	Value
Publication number	US-9673191-B2
Application number	US-201514659929-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Apr 16, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region.

First claim

The invention claimed is:

1. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:
a CMOS device in a CMOS region;
a PNP bipolar device in a bipolar region;
a spacer clear region defined by an opening in a common spacer layer over said CMOS region and said bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of said PNP bipolar device are formed in said spacer clear region, wherein a width of said sub-collector of said PNP bipolar device is substantially defined by said opening;
a collector sinker directly adjoining said spacer clear region and electrically connected to said sub-collector of said PNP bipolar device.

2. The BiCMOS device of claim 1 , wherein said base of said PNP bipolar device comprises silicon germanium (SiGe).

3. The BiCMOS device of claim 1 , wherein said sub-collector of said PNP bipolar device comprises a high energy spacer clear implant.

4. The BiCMOS device of claim 1 , further comprising an NPN bipolar device in said bipolar region.

5. The BiCMOS device of claim 4 , wherein said NPN bipolar device comprises a sub-collector, a selectively implanted collector and a base in another spacer clear region.

6. The BiCMOS device of claim 4 , wherein said base of said NPN bipolar device comprises silicon germanium (SiGe).

7. The BiCMOS device of claim 4 , wherein said NPN bipolar device comprises another collector sinker adjacent to another spacer clear region and electrically connected to a sub-collector of said NPN bipolar device.

8. The BiCMOS device of claim 1 , wherein said CMOS device is an N-channel field-effect transistor (NFET).

9. The BiCMOS device of claim 1 , wherein said common spacer layer comprises silicon nitride.

10. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:
a CMOS device in a CMOS region;
a PNP bipolar device in a bipolar region;
a spacer clear region defined by an opening in a common spacer layer over said CMOS region and said bipolar region, wherein a collector, and a base of said PNP bipolar device are formed in said spacer clear region, wherein a width of said collector of said PNP bipolar device is substantially defined by said opening;
a collector sinker directly adjoining said spacer clear region and electrically connected to said collector of said PNP bipolar device.

11. The BiCMOS device of claim 10 , wherein said base of said PNP bipolar device comprises silicon germanium (SiGe).

12. The BiCMOS device of claim 10 , further comprising an NPN bipolar device in said bipolar region.

13. The BiCMOS device of claim 12 , wherein said NPN bipolar device comprises a collector and a base in another spacer clear region.

14. The BiCMOS device of claim 12 , wherein said base of said NPN bipolar device comprises silicon germanium (SiGe).

15. The BiCMOS device of claim 12 , wherein said NPN bipolar device comprises another collector sinker adjacent to another spacer clear region and electrically connected to a collector of said NPN bipolar device.

16. The BiCMOS device of claim 10 , wherein said CMOS device is an N-channel field-effect transistor (NFET).

17. The BiCMOS device of claim 10 , wherein said common spacer layer comprises silicon nitride.

Assignees

• Newport Fab Llc

Inventors

• Preisler Edward
• Thibeault Todd

Classifications

• H10D84/401 Primary

  Combinations of FETs or IGBTs with BJTs · CPC title

• H01L29/161

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L27/102

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic