Metal to metal bonding for stacked (3D) integrated circuits

Patent metadata

Field	Value
Publication number	US-9673176-B2
Application number	US-201514958183-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Jan 9, 2013
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

First claim

What is claimed is:

1. A 3D structure comprising:
a bonding layer upon a copper metal surface, wherein an average grain size of the bonding layer is smaller than an average grain size of the copper metal surface, and wherein the copper metal surface is a surface of an interconnect that connects a first semiconductor die to a second semiconductor die; and
a metallic bond at an interface between the first interconnect and the second interconnect, the interface comprising a metal deposition inhibitor at a first concentration being at least one order of magnitude higher than a second concentration of the metal deposition inhibitor within the first interconnect and the second interconnect.

2. The 3D structure of claim 1 , wherein the bonding layer is electrolessly plated upon the copper metal surface.

3. The 3D structure of claim 1 , wherein the copper metal surface is rough.

4. The 3D structure of claim 1 , wherein the copper metal surface comprises a discontinuous seed layer.

5. The 3D structure of claim 1 , wherein the interconnect is a through substrate via.

6. The 3D structure of claim 1 , wherein the interconnect is a contact pad.

7. The 3D structure of claim 1 , wherein the interconnect is a Back End of Line metallization portion.

8. The 3D structure of claim 1 , wherein the bonding layer is a fine textured layer.

9. The 3D structure of claim 1 , wherein the average grain size of the bonding layer is less than one micron.

10. The 3D structure of claim 1 , wherein the average grain size of the bonding layer is less than 0.6 microns.

11. The 3D structure of claim 1 , wherein grains of the bonding layer resist self-annealing with grains of the copper metal surface.

12. A system comprising:
a interconnect that connects a first semiconductor die to a second semiconductor die, the interconnect comprising a bonding layer upon a copper metal surface, wherein an average grain size of the bonding layer is smaller than an average grain size of the copper metal surface; and
a metallic bond at an interface between the first interconnect and the second interconnect, the interface comprising a metal deposition inhibitor at a first concentration being at least one order of magnitude higher than a second concentration of the metal deposition inhibitor within the first interconnect and the second interconnect.

13. The system of claim 12 , wherein the bonding layer is electrolessly plated upon the copper metal surface.

14. The system of claim 12 , wherein the copper metal surface is rough.

15. The system of claim 12 , wherein the copper metal surface comprises a discontinuous seed layer.

16. The system of claim 12 , wherein the bonding layer is a fine textured layer.

17. The system of claim 12 , wherein the average grain size of the bonding layer is less than one micron.

18. The system of claim 12 , wherein the average grain size of the bonding layer is less than 0.6 microns.

19. The system of claim 12 , wherein grains of the bonding layer resist self-annealing with grains of the copper metal surface.

Assignees

• IBM

Inventors

• Cheng Tien-Jen
• Farooq Mukta G
• Fitzsimmons John A

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W80/334

  Thermocompression bonding · CPC title