Batch process for connecting chips to a carrier

Patent metadata

Field	Value
Publication number	US-9673170-B2
Application number	US-201414451868-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Aug 5, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

First claim

What is claimed is:

1. A method for forming chip arrangements, the method comprising:
placing chips on a transfer carrier;
placing the transfer carrier with the chips directly on a chip carrier;
after placing the transfer carrier on the chip carrier, forming connections between the chips and the chip carrier; and
removing the transfer carrier from the chips.

2. The method according to claim 1 , wherein forming the connections comprises forming the connections in a single heating step, in a single pressing step, or in a single heating and pressing step.

3. The method according to claim 1 , wherein the chips are vertical chips.

4. A method for connecting a plurality of chips to a chip carrier, the method comprising:
placing first chips on a transfer carrier, the first chips comprising chip frontside contacts on top sides of the chips and chip backside contacts on bottom sides of the chip;
placing second chips on the transfer carrier, the second chips comprising chip frontside contacts on top sides of the chips and no chip contacts on the bottom sides of the chips;
placing the transfer carrier with the bottom sides of the first and second chips on the chip carrier; and
forming first connections with a first connection medium between the bottom sides of the first chips and the chip carrier and forming second connections with a second connection medium between the bottom sides of the second chips and the chip carrier, wherein the first connection medium is an electrically insulating connection medium, and wherein the second connection medium is an electrically conductive connection medium.

5. The method according to claim 4 , wherein the electrically conductive connection medium comprises a solder, an electrically conductive paste, or an electrically conductive adhesive, and wherein the electrically insulating connection medium comprises an epoxy, a glue, a paste, a tape or a film.

6. The method according to claim 4 , wherein the chip carrier is a metal plate, wherein the metal plate comprises first and second chip islands, wherein the first and second chip islands are isolated from remaining portions of the metal plate, wherein the first connections are formed on the first chip islands, wherein the second connections are formed on the second chip islands, and wherein the first and second connection medium comprises a solder, an electrically conductive paste, or an electrically conductive adhesive.

7. The method according to claim 4 , further comprising removing the transfer carrier from the first and second chips after the first and second connections are formed.

8. A method for connecting a plurality of chips to a chip carrier, the method comprising:
placing first chips on a transfer carrier;
placing second chips on the transfer carrier, wherein the first chips are different from the second chips;
placing the transfer carrier with the first and second chips on the chip carrier; and
applying a pressure and a temperature in a single processing step thereby forming first connections between the first chips and the chip carrier and second connections between the second chips and the chip carrier,
wherein forming the first connections for the first chips comprises using an electrically insulating connection medium and forming the second connections for the second chips comprises using an electrically conductive connection medium.

9. The method according to claim 8 , further comprising removing the transfer carrier from the first and second chips after the first and second connections are formed.

10. The method according to claim 9 , further comprising separating the chip carrier thereby forming chip arrangements, each chip arrangement comprising a portion of the chip carrier, a first chip of the first chips and a second chip of the first chips.

11. The method according to claim 10 , further comprising packaging the chip arrangements.

12. The method according to claim 8 , further comprising forming first connection media on bottom sides of the first chips, and forming second connection media on the bottom sides of the second chips.

13. The method according to claim 8 , further comprising forming first connection media at die attach areas of the first chips on the chip carrier, and forming second connection media on bottom sides of the second chips.

14. The method according to claim 8 , wherein the transfer carrier is a transfer foil, and wherein the chip carrier is a lead frame or a metal plate.

15. The method according to claim 8 , wherein the chip carrier is a lead frame, and wherein the lead frame is a split lead frame comprising insulated die pads.

16. The method according to claim 8 , further comprising:
processing a first wafer with first devices having first electrodes only on single surfaces;
separating the first wafer thereby forming the first chips comprising the first devices having the first electrodes only on the single surfaces;
processing a second wafer with second devices having second electrode on opposite surfaces; and
separating the second wafer thereby forming the second chips comprising the second devices having the second electrodes on the opposite surfaces.

Assignees

• Infineon Technologies Ag

Inventors

• Fischer Rupert
• Strobel Peter
• Mahler Joachim
• Roesl Konrad
• Heinrich Alexander

Classifications

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title