Package structure having a laminated release layer and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9673140-B2
Application number	US-201514620328-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Apr 8, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

First claim

What is claimed is:

1. A method for fabricating a package structure, comprising the steps of:
providing a carrier having a plurality of bonding pads;
laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier, wherein the release portion has a first metal layer and a second metal layer stacked on and in physical contact with one another, the first metal layer is bonded to the bonding pads and the carrier, and a projection area of the second metal layer in a top view is less than a projection area of the first metal layer in the top view;
forming a plurality of conductive posts in the built-up portion; and
removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity.

2. The method of claim 1 , wherein the carrier is made of prepreg, polypropylene, glass fiber resin or polyimide.

3. The method of claim 1 , wherein forming the conductive posts comprises forming a plurality of through holes penetrating the built-up portion and filling a conductive material in the through holes to form the conductive posts.

4. The method of claim 1 , wherein the built-up portion has a circuit layer electrically connected to the conductive posts.

5. The method of claim 1 , further comprising disposing a stack member on the built-up portion, wherein the stack member is electrically connected to the conductive posts.

6. The method of claim 5 , wherein the stack member is a packaging substrate, a semiconductor chip, a silicon interposer or a package.

7. The method of claim 1 , wherein removing the release portion and the built-up portion on the release portion comprises the steps of:
laser cutting the built-up portion to remove a portion of the release portion and the built-up portion thereon; and
removing the remaining portion of the release portion by etching.

8. The method of claim 1 , further comprising disposing an electronic component in the cavity, wherein the electronic component is electrically connected to the bonding pads.

9. The method of claim 1 , wherein the built-up portion further comprises:
a dielectric layer that is in contact with the carrier and has an opening;
a supporting plate formed on the dielectric layer.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Chia-Cheng
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chiu Shih-Chao
• Hsiao Wei-Chung
• Pai Yu-Cheng
• Jiang Don-Son

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title