Dynamic data caches, decoders and decoding methods

Patent metadata

Field	Value
Publication number	US-9672156-B2
Application number	US-201615083130-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	May 12, 2011
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

First claim

What is claimed is:

1. A memory device having a dynamic data cache (DDC) region including a DDC, the memory device comprising:
a plurality of data lines, wherein each of the plurality of data lines traverses the DDC region, wherein the plurality of data lines comprises a plurality of bytes of data lines;
a plurality of byte select lines, wherein each of the byte select lines is configured to select a respective one of the plurality of bytes of data lines;
a single column select line configured to select the plurality of bytes of data lines; and
a single verify line corresponding to the DDC, wherein the verify line does not run parallel to the data lines as it traverses the DDC region, wherein the verify line is configured to verify data stored in the DDC.

2. The memory device of claim 1 , wherein the verify line is perpendicular to the plurality of data lines.

3. The memory device of claim 1 , wherein the plurality of byte select lines do not run parallel to the data lines as they traverse the DDC region.

4. The memory device of claim 3 , wherein each of the plurality of byte select lines are perpendicular to the plurality of bytes of data lines.

5. A memory device having a dynamic data cache (DDC) region including a DDC, the memory device comprising:
a plurality of bytes of data lines, wherein each of the plurality of data lines traverses the DDC region;
a single column select line configured to select the plurality of bytes of data lines; and
a plurality of byte select lines, wherein each of the byte select lines is configured to select a respective one of the plurality of bytes of data lines, wherein each of the plurality of byte select lines do not run parallel to the plurality of bytes of data lines as they traverse the DDC region.

6. The memory device of claim 5 , wherein each of the plurality of byte select lines are perpendicular to the plurality of bytes of data lines.

7. The memory device of claim 5 , further comprising a single verify line corresponding to the DDC.

8. A memory device having a dynamic data cache (DDC) region including a DDC, the memory device comprising:
a plurality of bytes of data lines, wherein each of the plurality of data lines traverses the DDC region;
a single column select line configured to select the plurality of bytes of data lines;
a plurality of byte select lines, wherein each of the byte select lines is configured to select a respective one of the plurality of bytes of data lines; and
a single verify line corresponding to the DDC, wherein the single verify line does not run parallel to the plurality of bytes of data lines as it traverses the DDC region.

9. The memory device of claim 8 , wherein the verify line is perpendicular to the plurality of bytes of data lines.

10. A memory device having a dynamic data cache (DDC) region including a DDC, the memory device comprising:
a dynamic data cache (DDC) region comprising a plurality of DDCs;
a plurality of data lines, wherein each of the plurality of data lines traverses the DDC region;
a single column select line configured to select the plurality of data lines; and
a single verify line corresponding to the plurality of DDCs,
wherein the single verify line does not parallel to the plurality of data lines as it traverses the DDC region, and
wherein the plurality of data lines couple a first memory array to a second memory array, and wherein the plurality of DDCs in the DDC region are configured to store data read from or programmed into either the first memory array or the second memory array.

11. The memory device of claim 10 , wherein each of the plurality of data lines is coupled to at least one of the plurality of DDCs via a transistor.

12. The memory device of claim 10 , wherein each of the plurality of data lines comprises a plurality of bytes of data lines.

13. The memory device of claim 12 , wherein the single column select line is configured to select the plurality of bytes of data lines.

14. The memory device of claim 12 , further comprising a plurality of byte select lines, wherein each of the byte select lines is configured to select a respective one of the plurality of bytes of data lines.

15. The memory device of claim 10 , wherein the verify line is configured to verify data stored in the DDC region.

16. A memory device having a dynamic data cache (DDC) region including a DDC, the memory device comprising:
a dynamic data (DDC) region comprising a plurality of DDCs;
a plurality of data lines, wherein each of the plurality of data lines traverses the DDC region;
a plurality of byte select lines, wherein each of the byte select lines is configured to select a respective one of the plurality of bytes of data lines;
a single column select line configured to select the plurality of data lines; and
a single verify line corresponding to the plurality of DDCs,
wherein each of the plurality of data lines comprises a plurality of bytes of data lines,
wherein the plurality of data lines couple a first memory array to a second memory array, and wherein the plurality of DDCs in the DDC region are configured to store data read from or programmed into either the first memory array or the second memory array, and
wherein the plurality of byte select lines do not run parallel to the data lines as they traverse the DDC region.

Assignees

• Micron Technology Inc

Inventors

• Ha Chang Wan

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title