Dynamic data caches, decoders and decoding methods

Patent metadata

Field	Value
Publication number	US-9299442-B2
Application number	US-201414262308-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	May 12, 2011
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

First claim

What is claimed is:

1. A cache access circuit comprising:
a data input/output line;
a cache line;
a first transistor having a source/drain terminal coupled to the data input/output line, wherein the first transistor is configured to receive a first select signal at its gate terminal; and
a second transistor having a first source/drain terminal coupled to the source/drain terminal of the first transistor and a second source/drain terminal coupled to the cache line, wherein the second transistor is configured to receive a second select signal at its gate terminal;
wherein the first select signal is configured to select a group of bytes, and the second select signal is configured to select a particular byte within the group of bytes.

2. The cache access circuit of claim 1 , wherein the data input/output line and the cache line are differential lines.

3. The cache access circuit of claim 1 , wherein the first and second transistors are configured to couple the data input/output line to the cache line responsive to a combination of the first and second select signals.

4. The cache access circuit of claim 1 , further comprising a pair of cross coupled inverters coupled to the cache line.

5. The cache access circuit of claim 1 , wherein the cache line is coupled to a secondary data cache.

6. The cache access circuit of claim 1 , further comprising:
a first select line configured to provide the first select signal to the gate terminal of the first transistor; and
a second select lines configured to provide the second select signal to the gate terminal of the second transistor, wherein the first select line is perpendicular to the second select line.

7. A method for accessing a dynamic data cache, the method comprising:
decoding a first signal from a plurality of column select signals, wherein the act of decoding comprises providing the plurality of column select signals to a NOR gate;
providing the first signal configured to select a plurality of bytes of the dynamic data cache to an access circuit;
providing a second signal configured to select one of the bytes of the plurality of bytes to the access circuit;
wherein a data input/output line is coupled to a data cache responsive to both the first and second signals.

8. The method of claim 7 , wherein said providing a first signal comprises applying the first signal to a first select line, and wherein said providing a second signal comprises applying the second signal to a second select line.

9. An apparatus comprising:
a first transistor coupled to a data line, wherein the first transistor is configured to be enabled responsive to a first signal;
a second transistor coupled between the first transistor and a cache line, wherein the second transistor is configured to be enabled responsive to a second signal;
a third transistor coupled to a second data line, wherein the third transistor is configured to be enabled responsive to the first signal; and
a fourth transistor coupled between the third transistor and a second cache line, wherein the second transistor is configured to be enabled responsive to the second signal,
wherein a combination of the first signal and the second signal selects a particular byte of a group of bytes.

10. The apparatus of claim 9 , wherein the first data line and the second data line are configured to provide complementary data.

11. The apparatus of claim 9 , further comprising:
a first inverter coupled to the first cache line, wherein the first inverter includes a fifth transistor having a gate coupled to the second cache line; and
a second inverter coupled between the first inverter and the second cache line, wherein the second inverter includes a sixth transistor having a gate coupled to the first cache line.

12. The apparatus of claim 11 , wherein the first inverter includes a seventh transistor coupled between the first cache line and the fifth transistor, the seventh transistor configured to be enabled via a read signal, wherein the second inverter includes an eighth transistor coupled between the second cache line and the sixth transistor, the sixth transistor configured to be enabled via the read signal.

13. The apparatus of claim 12 , wherein the first and second inverters are cross-coupled.

14. The apparatus of claim 9 , wherein the first transistor and the second transistor are configured to couple the data line to the cache line responsive to the first signal and the second signal.

15. The apparatus of claim 9 , further comprising:
a first select line configured to provide the first signal; and
a second select line configured to provide the second signal.

16. The apparatus of claim 15 , wherein the first select line is perpendicular to the second select line.

17. The apparatus of claim 9 , wherein the first transistor is an n-type transistor and the second transistor is an n-type transistor.

18. The apparatus of claim 9 , wherein the first transistor and the second transistor included in a dynamic data cache of a flash memory device.

Assignees

• Micron Technology Inc
• Micron Technologies Inc

Inventors

• Ha Chang Wan

Classifications

• G11C8/10 Primary

  Decoders · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F2212/3042

  being part of a memory device, e.g. cache DRAM · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title