Methods and apparatus for transforming, loading, and executing super-set instructions

Patent metadata

Field	Value
Publication number	US-9672033-B2
Application number	US-35061009-A
Country	US
Kind code	B2
Filing date	Jan 8, 2009
Priority date	Nov 10, 2004
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from program memory to be transformed into a new language format and then loaded into a transformed instruction memory. The format of the transformed instruction may be optimized to the implementation requirements, such as improving critical path timing. The transformation of instructions may extend to other needs beyond timing path improvement, for example, requiring super-set instructions for increased functionality and improvements to instruction level parallelism. Techniques for transforming, loading, and executing super-set instructions are described.

First claim

We claim:

1. An instruction transform apparatus for transforming an instruction to a new form, the instruction transform apparatus comprising:
an instruction cache storing instructions from which a sequence of instructions are fetched to form a very long instruction word (VLIW);
a first instruction register for receiving the fetched sequence of instructions, the fetched sequence beginning with a decode and load instruction followed by a second instruction, wherein the decode and load instruction causes the second instruction to be transformed into a partially decoded form, wherein the second instruction is comprised of a first bit field, a second bit field, and other instruction bits, wherein a bit field represents specified bits in a preselected bit field;
a first decode unit connected to the first instruction register selectively determining to decode the first bit field of the second instruction to a first decoded full machine level format set of bits, selectively determining to decode the second bit field of the second instruction to a second decoded full machine level format set of bits, wherein the selectively determining to decode or to not decode is in response to a specification encoded in the second instruction and wherein a transformed partially decoded form of the second instruction is created to include the other instruction bits which are not decoded, the first decoded full machine level format set of bits, and the second decoded full machine level format set of bits; and
a transform storage unit for storing the transformed partially decoded form of the second instruction in an instruction slot of the VLIW at an address generated in response to the decode and load instruction, wherein the bit width of the transformed partially decoded form of the second instruction depends upon the selectively determining to decode or to not decode.

2. The instruction transform apparatus of claim 1 further comprising:
a second decode unit to decode bit fields not previously decoded in the transformed partially decoded form of the second type instruction to form an execution unit capable instruction;
a decode register for storing the execution unit capable instruction and having
a decoded output from the decode register.

3. The instruction transform apparatus of claim 2 further comprising:
an execution unit coupled to the decoded output and capable of receiving and executing the execution unit capable instruction.

4. The instruction transform apparatus of claim 1 further comprising:
a program storage unit for storing the decode and load instruction and the second instruction in sequential fetch order.

5. The instruction transform apparatus of claim 1 wherein each instruction of the sequence of instructions is a 16-bit instruction having a bit that indicates whether the 16-bit instruction is a control instruction for execution on a control processor or a processing element instruction for execution on one or more of a plurality of processing elements.

6. The instruction transform apparatus of claim 1 further comprising:
a second instruction register for storing the transformed partially decoded form of the second instruction that was decoded in the first decode unit; and
an instruction selector for selecting the transformed partially decoded form of the second instruction from the second instruction register or the transformed partially decoded form of the second instruction fetched from the transform storage unit for final decoding and execution.

7. The instruction transform apparatus of claim 6 wherein the instruction selector selects the transformed partially decoded form of the second instruction from the transform storage unit in response to an execute VLIW instruction.

8. A method of storing a partially decoded instruction into a very long instruction word (VLIW) storage unit, the method comprising:
fetching a sequence of instructions from an instruction cache, wherein each instruction of the sequence of instructions is used to form a VLIW;
receiving the fetched sequence of instructions in a first instruction register, the fetched sequence beginning with a decode and load instruction followed by a second instruction, wherein the decode and load instruction causes the second instruction to be transformed into a partially decoded format, wherein the second instruction is comprised of a first bit field, a second bit field, and other instruction bits, wherein a bit field represents specified bits in a preselected bit field;
selectively determining to decode the first bit field of the second instruction to a first decoded full machine level format set of bits, selectively determining to decode the second bit field of the second instruction to a second decoded full machine level format set of bits, in a first decode unit connected to the instruction register, wherein the selectively determining to decode or to not decode is in response to a specification encoded in the second instruction;
configuring a transformed partially decoded form of the second instruction by replacing the first bit field of the second instruction with the first decoded full machine level format set of bits, replacing the second bit field of the second instruction with the second decoded full machine level format set of bits, and including the other instruction bits of the second instruction; and
storing in an instruction slot of the VLIW of a transform storage unit the transformed partially decoded form of the second instruction at an address generated in response to the decode and load instruction, wherein the bit width of the transformed partially decoded form of the second instruction depends upon the selectively determining to decode or to not decode.

9. The method of claim 8 further comprising:
decoding in a second decode unit the transformed partially decoded form of the second instruction into an execution unit capable instruction; and
storing the execution unit capable instruction in a binary machine code decode register.

10. The method of claim 8 further comprising:
storing the decode and load instruction and the second instruction in sequential fetch order in a program storage unit.

11. The method of claim 8 wherein each of the sequence of instructions is a 16-bit instruction having a bit that indicates whether the 16-bit instruction is a control instruction for execution on a control processor or a processing element instruction for execution on one or more of a plurality of processing elements.

12. The method of claim 8 further comprising:
storing the transformed partially decoded form of the second instruction that was decoded in the first decode unit in a second instruction register; and
selecting in an instruction selector the transformed partially decoded form of the second instruction from the second instruction register or the transformed partially decoded form of the second instruction fetched from the transform storage unit for final decoding and execution.

13. The method of claim 12 wherein the instruction selector selects the transformed partially decoded form of the second instruction from the transform storage unit in response to an execute VLIW instruction.

14. A method for storing a partially decoded instruction in a slot in a VLIW storage, the method comprising:
fetching a decode and load instruction from an instruction cache to an instruction register, the decode and load instruction having an instruction count parameter set at least to a value two;
decoding the decode and load instruction stored in the instruction register to set a VLIW mode bit to indicate that a VLIW decode and load is active;
generating

Assignees

• Pechanek Gerald George
• Larsen Larry D
• Altera Corp

Inventors

• Pechanek Gerald George
• Larsen Larry D

Classifications

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title