Sharing an accelerator context across multiple processes

Patent metadata

Field	Value
Publication number	US-9671970-B2
Application number	US-201514923885-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a shared memory space, a system creates a shared hardware context on the coherent hardware accelerator and binds the first process and the shared memory space to the hardware context. In response to the first process spawning one or more second processes, the system binds the one or more second processes to the shared memory space and the hardware context. Subsequently, the system performs one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

First claim

What is claimed is:

1. A computer program product, comprising:
a computer-readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to perform an operation for sharing, by multiple processes, a hardware context established on a coherent hardware accelerator, the operation comprising:
in response to using a first process:
creating a shared memory space,
creating a shared hardware context on the coherent hardware accelerator,
attaching the shared memory space to the shared hardware context, and
binding the first process to the shared hardware context;

in response to the first process spawning one or more second processes, binding the one or more second processes to the shared memory space and the hardware context; and
performing one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

2. The computer program product of claim 1 , wherein creating the shared hardware context comprises:
generating a key identifying the shared hardware context;
and providing the key to the first process.

3. The computer program product of claim 2 , wherein binding the one or more second processes to the shared hardware context comprises allowing the one or more second processes to access the shared memory space attached to the shared hardware context.

4. The computer program product of claim 1 , wherein creating the shared hardware context comprises launching a kernel process associated with the shared hardware context to resolve faults generated while performing operations on the coherent hardware accelerator.

5. The computer program product of claim 1 , wherein the operations further comprise:
detecting a page fault generated by an operation executed on the coherent accelerator by one of the first process or one or more second processes; and
resolving the page fault.

6. The computer program product of claim 5 , wherein the kernel process is configured to process multiple page faults simultaneously.

7. A system, comprising:
a processor; and
memory storing one or more instructions which, when executed by the processor, performs an operation for sharing, by multiple processes, a hardware context established on a coherent hardware accelerator, the operation comprising:
using a first process:
creating a shared memory space,
creating a shared hardware context on the coherent hardware accelerator,
attaching the shared memory space to the shared hardware context, and
binding the first process to the shared hardware context;

in response to the first process spawning one or more second processes, binding the one or more second processes to the shared memory space and the hardware context; and
performing one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

8. The system of claim 7 , wherein creating the shared hardware context comprises:
generating a key identifying the shared hardware context;
and providing the key to the first process.

9. The system of claim 8 , wherein binding the one or more second processes to the shared hardware context comprises allowing the one or more second processes to access the shared memory space attached to the shared hardware context.

10. The system of claim 7 , wherein creating the shared hardware context comprises launching a kernel process associated with the shared hardware context to resolve faults generated while performing operations on the coherent hardware accelerator.

11. The system of claim 7 , wherein the operations further comprise:
detecting a page fault generated by an operation executed on the coherent accelerator by one of the first process or one or more second processes; and
resolving the page fault using a kernel process.

12. The system of claim 11 , wherein resolving the page fault comprises:
loading a memory page associated with an address that caused the page fault into the shared memory space.

13. The system of claim 11 , wherein the kernel process is configured to process multiple page faults simultaneously.

Assignees

• IBM

Inventors

• Mealey Bruce
• Rogers Mark D

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F3/0631 Primary

  by allocating resources to storage systems · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title