Integrated hall effect sensor with a biased buried electrode

Patent metadata

Field	Value
Publication number	US-9671473-B2
Application number	US-201414286431-A
Country	US
Kind code	B2
Filing date	May 23, 2014
Priority date	May 30, 2013
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.

First claim

What is claimed is:

1. A method for generating a Hall voltage within a semiconductor film disposed on top of an insulating layer which is disposed on top of a carrier semiconductor substrate containing a buried semiconductor electrode situated under the insulating layer, comprising:
flowing a current within the semiconductor film that is subjected to a magnetic field, and
biasing the buried semiconductor electrode with a bias voltage by applying the bias voltage to the carrier semiconductor substrate which is in electrical contact with the buried semiconductor electrode.

2. The method according to claim 1 , wherein the semiconductor film includes a dopant concentration level greater than for an intrinsic semiconductor material, and wherein biasing comprises biasing the buried semiconductor electrode with a bias voltage chosen so as to reduce the dopant concentration level.

3. The method according to claim 2 , wherein biasing comprises biasing the buried semiconductor electrode with a bias voltage chosen so as to reduce the dopant concentration level to substantially equal a dopant concentration level of intrinsic semiconductor material.

4. The method according to claim 1 , wherein the buried semiconductor electrode is a doped region of the carrier semiconductor substrate situated under the insulating layer.

5. A method for generating a Hall voltage within a semiconductor film disposed on top of an insulating layer which is disposed on top of a carrier semiconductor substrate containing a buried semiconductor electrode situated under the insulating layer, comprising:
flowing a current within the semiconductor film that is subjected to a magnetic field;
biasing the buried semiconductor electrode with a bias voltage;
measurement of the Hall voltage generated within the semiconductor film;
determining a current flowing through a metallization disposed near the semiconductor film;
wherein the magnetic field to which the semiconductor film is subjected arises from the magnetic field generated by the flow of the current within the metallization; and
determining the magnetic field and the current flowing through the metallization based on the value of the magnetic field.

6. The method according to claim 5 , wherein biasing the buried semiconductor electrode comprises applying the bias voltage to the carrier semiconductor substrate which is in electrical contact with the buried semiconductor electrode.

7. The method according to claim 5 , wherein the semiconductor film includes a dopant concentration level greater than for an intrinsic semiconductor material, and wherein biasing comprises biasing the buried semiconductor electrode with a bias voltage chosen so as to reduce the dopant concentration level.

8. The method according to claim 7 , wherein biasing comprises biasing the buried semiconductor electrode with a bias voltage chosen so as to reduce the dopant concentration level to substantially equal a dopant concentration level of intrinsic semiconductor material.

9. The method according to claim 5 , wherein the buried semiconductor electrode is a doped region of the carrier semiconductor substrate situated under the insulating layer.

10. An integrated Hall effect sensor, comprising:
a substrate of the silicon-on-insulator type comprising a semiconductor film disposed on top of an insulating layer which is disposed on top of a carrier semiconductor substrate;
a buried semiconductor electrode disposed in a region of the carrier semiconductor substrate under the region of the insulating layer;
a first metal connection coupled to a first area of the semiconductor film and configured to receive a current;
a second metal connection coupled to a second area of the semiconductor film and configured to deliver the current having passed through the semiconductor film;
a third metal connection coupled to a third area of the semiconductor film and configured to deliver a Hall voltage; and
a biasing connection configured to apply a biasing voltage to the carrier semiconductor substrate for biasing the buried semiconductor electrode.

11. The sensor according to claim 10 , wherein the semiconductor film has a first level of dopant concentration in the absence of biasing of the buried electrode that is greater than a second level of dopant concentration of intrinsic semiconductor material.

12. The sensor according to claim 11 , wherein the semiconductor film has third level of dopant concentration in the presence of biasing of the buried electrode that is between the first dopant concentration and the second dopant concentration.

13. The sensor according to claim 12 , wherein the third dopant concentration of the semiconductor film in the presence of biasing of the buried electrode is substantially equal to the second dopant concentration of intrinsic semiconductor material.

14. The sensor according to claim 10 , wherein the substrate is a fully-depleted substrate on insulator.

15. The sensor according to claim 10 as fabricated as an integrated circuit.

16. The sensor according to claim 15 , further comprising:
at least one integrated circuit component;
a metallization coupled to the integrated circuit component disposed adjacent the sensor and configured to carry a current in such a manner as to generate a magnetic field within the sensor; and
a determination circuit configured to determine the current flowing within the metallization.

17. The sensor according to claim 10 , wherein the buried semiconductor electrode is a doped region of the carrier semiconductor substrate.

18. An apparatus, comprising:
a supporting substrate including:
a first region of semiconductor material of a first conductivity type and a second region of semiconductor material of a second conductivity type, the first and second regions isolated from each other by an isolation region;

a Hall effect sensor formed over the first region, said sensor comprising:
a buried electrode in contact with the first region;
an insulating layer formed over the buried electrode;
a semiconductor film formed over the insulating layer; and
first and second electrical contacts disposed on the semiconductor film; and

a biasing circuit comprising an electrical contact made with the first region and configured to receive a biasing voltage for application to said buried electrode.

19. The apparatus of claim 18 , further comprising: an integrated structure formed over the second region, said structure comprising:
an additional buried electrode in contact with the second region;
an additional insulating layer formed over the additional buried electrode; and
an additional semiconductor film formed over the additional insulating layer; and
an additional biasing circuit comprising an additional electrical contact made with the second region.

20. The apparatus of claim 19 , wherein the additional semiconductor film supports formation of integrated circuits.

21. The apparatus of claim 18 , wherein the buried electrode is a doped region of the first region of semiconductor material under the insulating layer.

Assignees

• St Microelectronics Sa

Inventors

• Trochut Severin
• Remond Eric

Classifications

• G01R33/072 Primary

  Constructional adaptation of the sensor to specific applications · CPC title

• H01L43/065

  Electricity · mapped topic

• H01L43/04

  Electricity · mapped topic

• H10N52/101

  Semiconductor Hall-effect devices · CPC title

• H10N52/80

  Constructional details · CPC title