Reproducible step-edge Josephson junction

Patent metadata

Field	Value
Publication number	US-9666783-B2
Application number	US-201314389839-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Apr 4, 2012
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy. By orienting the same crystal axis in each case perpendicularly to the step edge on both sides of the step edge, a maximal supercurrent can flow across the grain boundary induced by the step edge, and consequently across the Josephson junction.

First claim

The invention claimed is:

1. A component comprising a Josephson junction, comprising:
a substrate comprising at least one step edge on a textured surface thereof and
a functional layer made of a high-temperature superconducting material disposed on the textured surface of the substrate such that the functional layer also comprises at least one step edge,
wherein a grain boundary that forms a weak link of the Josephson junction is present at the at least one step edge of the functional layer,
wherein texturedness of the textured surface of the substrate and/or at least one first textured buffer layer disposed between the substrate and the functional layer causes, on both sides of the at least one step edge of the functional layer, an a crystal axis or a b crystal axis or both crystal axes in a plane of the functional layer to be oriented perpendicularly to the grain boundary to within a deviation of no more than 10°
wherein the textured surface of the substrate and/or the at least one first textured buffer layer comprises elevations and/or depressions having an average height or depth of between 1 nm and 10 nm.

2. A component comprising a Josephson junction, comprising:
a substrate comprising at least one step edge on a textured surface thereof and
a functional layer made of a high-temperature superconducting material disposed on the surface of the substrate such that the functional layer also comprises at least one step edge,
wherein a grain boundary that forms a weak link of the Josephson junction is present at the at least one step edge of the functional layer,
wherein the functional layer is grown on the textured surface of the substrate and/or on a textured buffer layer disposed between the substrate and the functional layer by graphoepitaxy,
wherein texturedness of the textured surface of the substrate on both sides of the step edge of the substrate causes an a crystal axis or a b crystal axis or both crystal axes in a plane of the functional layer to be oriented perpendicularly to the grain boundary to within a deviation of no more than 10°.

3. The component according to claim 1 , wherein an anti-epitaxial buffer layer is disposed between the functional layer and the substrate, wherein the anti-epitaxial buffer layer is either amorphous or has a crystal structure that is not epitaxy-compatible with the substrate and/or with the functional layer, so that a c-axis of the functional layer is perpendicular to a surface of the anti-epitaxial buffer layer to within a deviation of no more than 10°.

4. The component according to claim 3 , wherein the anti-epitaxial buffer layer has a thickness of 10 nm or less.

5. The component according to claim 3 , wherein each lattice constant of the anti-epitaxial buffer layer in its layer plane is closer to lattice constants a and b in the plane of the functional layer than to any integer multiple or divisor of lattice constant c of the anti-epitaxial buffer layer.

6. The component according to claim 3 , wherein the anti-epitaxial buffer layer is textured.

7. The component according to claim 3 , wherein a second textured buffer layer is disposed between the substrate and the anti-epitaxial buffer layer, or between the anti-epitaxial buffer layer and the functional layer.

8. The component according to claim 1 , wherein the at least one first textured buffer layer is disposed as an only buffer layer directly between the substrate and the functional layer.

9. The component according to claim 7 , wherein the at least one first textured buffer layer is at least 20% thicker than the anti-epitaxial buffer layer.

10. The component according to claim 7 , wherein the at least one first textured buffer layer has a thickness of 10 nm or less.

11. The component according to claim 7 , wherein the at least one first textured buffer layer has a lattice constant in a plane thereof ranging between 90% and 100% of a lattice constant of the functional layer along the a-axis or the b-axis in the plane of the functional layer.

12. The component according to claim 7 , wherein texturedness of the textured surface of the substrate and/or the at least one first textured buffer layer comprises elevations and/or depressions having an average height or depth between 1 nm and 10 nm.

13. The component according to claim 1 , wherein a radius of curvature of the substrate at the at least one step edge is 10 nm or less.

14. The component according to claim 1 , wherein the at least one step edge separates a planar surface region from a curved surface region.

15. The component according to claim 14 , wherein a radius of curvature of the curved surface region is 10 nm or more.

16. The component according to claim 1 , comprising a step region which separates two planar regions of the substrate having a first orientation, and is tilted with respect to the two planar regions, such that the functional layer assumes a different, but constant crystal orientation in the step region.

17. The component according to claim 1 , wherein the textured surface of the substrate at the at least one step edge is bent by an angle between 20° and 60°.

18. The component according to claim 1 , wherein the texturedness is rectangular or linear.

19. The component according to claim 1 , wherein the substrate is textured, and a further seed layer made of a material which is same as that of the functional layer is disposed between the substrate and the functional layer,
wherein texturedness of the substrate causes an a crystal axis or a b crystal axis, or both crystal axes in a plane of the seed layer to be oriented perpendicularly to the grain boundary to within a deviation of no more than 10° on both sides of the at least one step edge of the functional layer, and a barrier layer, which is impervious to at least one metallic or semiconducting element of the substrate, is disposed between the seed layer and the functional layer.

20. The component according to claim 19 , wherein the seed layer is configured to be normally conducting.

21. The component according to claim 19 , wherein the seed layer has a thickness of no more than 50 nm.

22. The component according to claim 19 , wherein the seed layer has a thickness of no more than ⅓ of a thickness of the functional layer.

23. The component according to claim 19 , wherein the barrier layer has a thickness between 1 nm and 1 μm.

24. The component according to claim 19 , wherein the barrier layer has a perovskite structure.

25. A detector or generator for THz radiation or a superconducting quantum interference device (SQUID) comprising at least one component according to claim 1 .

26. A method for producing a component comprising a Josephson junction from a substrate having at least one step edge on a surface thereof, the method comprising:
applying a high-temperature superconducting functional layer to the surface so as to extend on both sides of the at least one step edge, such that the functional layer also has at least one step edge,
wherein the substrate is textured and/or a textured buffer layer is applied to the substrate, and
wherein the functional layer is applied by way of graphoepitaxy so that a grain boundary is formed at the step edge of the functional layer and an a-axis or a b-axis or both axes thereof is/are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of texturing of the substrate and/or the textured

Assignees

• Forschungszentrum Juelich Gmbh

Inventors

• Faley Mikhail

Classifications

• H01L39/225

  Electricity · mapped topic

• H01L39/126

  Electricity · mapped topic

• H01L39/2496

  Electricity · mapped topic

• H01L39/2461

  Electricity · mapped topic

• H01L39/025 Primary

  Electricity · mapped topic