Manufacturing method of forming a semiconductor wafer structure

Patent metadata

Field	Value
Publication number	US-9666555-B2
Application number	US-201615203045-A
Country	US
Kind code	B2
Filing date	Jul 6, 2016
Priority date	Feb 12, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing a first wafer including a surface;
removing some portions of the first wafer to form a plurality of recesses extended over at least a portion of the surface of the first wafer;
providing a second wafer; and
disposing the second wafer over the surface of the first wafer.

2. The method of claim 1 , wherein the removing some portions of the first wafer includes etching or laser operation.

3. The method of claim 1 , wherein the disposing the second wafer includes bonding the second wafer with the first wafer.

4. The method of claim 3 , wherein the bonding the second wafer with the first wafer includes direct bonding operation, fusion bonding operation, eutectic wafer bonding operation or adhesive wafer bonding operation.

5. The method of claim 1 , wherein the first wafer is aligned with the second wafer before disposing the second wafer.

6. The method of claim 1 , wherein the disposing the second wafer includes applying a pressure over the second wafer towards the first wafer or applying a pressure over the first wafer towards the second wafer.

7. The method of claim 1 , wherein the disposing the second wafer includes forming a plurality of passages disposed between the first wafer and the second wafer and elongated over at least the portion of the first wafer.

8. The method of claim 1 , wherein the removing some portions of the first wafer includes disposing a photoresist on the surface and exposing the photoresist through a photomask with a predetermined pattern corresponding to positions of the plurality of recesses.

9. The method of claim 8 , wherein the removing some portions of the first wafer includes removing some portions of the first wafer exposed from the photomask.

10. The method of claim 1 , wherein each of the plurality of recesses is extended from a first side of the first wafer towards a second side of the first wafer opposite to the first side of the first wafer.

11. A method of manufacturing a semiconductor structure, comprising:
providing a first wafer;
removing some portions of the first wafer to form a plurality of protrusions protruded from the first wafer and elongated over at least a portion of the first wafer;
providing a second wafer; and
disposing the second wafer over the plurality of protrusions.

12. The method of claim 11 , wherein top surfaces of the plurality of protrusions are interfaced with the second wafer.

13. The method of claim 11 , wherein the first wafer is carrier wafer or a handle wafer.

14. The method of claim 11 , wherein the second wafer is a device wafer.

15. The method of claim 11 , wherein the disposing the second wafer includes forming a plurality of passages elongated over at least the portion of the first wafer, and each of the plurality of passages is disposed between two of the plurality of protrusions.

16. A method of manufacturing a semiconductor structure, comprising:
providing a first wafer;
forming a plurality of protrusions over the first wafer;
providing a second wafer; and
disposing the second wafer over the plurality of protrusions to form a plurality of passages elongated over at least a portion of the first wafer.

17. The method of claim 16 , wherein the disposing the second wafer includes forming a plurality of openings disposed at a periphery of the first wafer or a periphery of the second wafer.

18. The method of claim 17 , wherein the plurality of passages is extended from the plurality of openings respectively.

19. The method of claim 16 , wherein each of the plurality of passages is extended from a periphery of the first wafer towards a center of the first wafer or extended from a periphery of the second wafer towards a center of the second wafer.

20. The method of claim 16 , wherein the plurality of passages are elongated across the first wafer or the second wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chen-Chun
• Chen Chiu-Jung
• Tsai Fu-Tsun
• Jangjian Shiu-Ko
• Jeng Chi-Cherng
• Chen Hsin-Chi

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P90/126

  by chemical etching · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/642

  Chemical etching · CPC title