Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief

Patent metadata

Field	Value
Publication number	US-9666500-B2
Application number	US-201514697352-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Dec 14, 2007
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer;
forming a first insulating layer over the semiconductor wafer;
forming a second insulating layer over the first insulating layer; and
singulating the semiconductor wafer into a plurality of semiconductor die.

2. The method of claim 1 , further including:
forming a conductive layer over the semiconductor wafer; and
forming the first insulating layer over the conductive layer.

3. The method of claim 1 , further including:
forming a conductive layer over the first insulating layer; and
forming the second insulating layer over the conductive layer.

4. The method of claim 1 , further including forming an interconnect structure over the semiconductor die.

5. The method of claim 1 , further including:
removing the second insulating layer; and
forming a third insulating layer over the first insulating layer.

6. The method of claim 5 , wherein the third insulating layer provides stress relief.

7. A method of making a semiconductor device, comprising:
providing a semiconductor wafer;
forming a first insulating layer over the semiconductor wafer; and
forming a second insulating layer over the semiconductor wafer, wherein the first insulating layer or second insulating layer provides stress relief.

8. The method of claim 7 , further including singulating the semiconductor wafer through the first and second insulating layers and into a plurality of semiconductor die.

9. The method of claim 8 , further including depositing an encapsulant over the semiconductor die.

10. The method of claim 8 , further including forming an interconnect structure over the semiconductor die.

11. The method of claim 7 , further including:
removing the second insulating layer; and
forming a third insulating layer over the first insulating layer.

12. The method of claim 7 , further including:
forming a channel in the semiconductor wafer; and
forming the second insulating layer in the channel.

13. A semiconductor device, comprising:
a semiconductor wafer including a channel formed in the semiconductor wafer;
a first insulating layer formed over the semiconductor wafer; and
a second insulating layer formed over the semiconductor wafer and in the channel.

14. The semiconductor device of claim 13 , wherein the first insulating layer or the second insulating layer provides stress relief.

15. The semiconductor device of claim 13 , further including:
a conductive layer formed over the semiconductor wafer; and
the first insulating layer formed over the conductive layer.

16. The semiconductor device of claim 13 , further including:
a conductive layer formed over the first insulating layer; and
the second insulating layer formed over the conductive layer.

17. The semiconductor device of claim 13 , wherein the second insulating layer includes a planar surface over the semiconductor wafer.

18. A semiconductor device, comprising:
a semiconductor die;
a first insulating layer formed over the semiconductor die; and
a second insulating layer formed over the semiconductor die with the first and second insulating layers remaining within a footprint of the semiconductor die, wherein the second insulating layer is configured to be removed from over the semiconductor die.

19. The semiconductor device of claim 18 , further including an encapsulant deposited over the semiconductor die and the first insulating layer.

20. The semiconductor device of claim 19 , further including an interconnect structure formed over the semiconductor die and the encapsulant.

21. The semiconductor device of claim 18 , wherein the first insulating layer or the second insulating layer provides stress relief.

22. The semiconductor device of claim 18 , further including:
a first conductive layer formed over the first insulating layer; and
the second insulating layer formed over the first conductive layer.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Marimuthu Pandi C
• Chen Kang
• Goh Hin Hwa
• GU Yu
• Shim Il Kwon
• Huang Rui
• Chow Seng Guan
• Fang Jianmin
• Feng Xia

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title