Methods of forming wiring structures and methods of manufacturing semiconductor devices

US9666478B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9666478-B2
Application numberUS-201615048993-A
CountryUS
Kind codeB2
Filing dateFeb 19, 2016
Priority dateMay 8, 2015
Publication dateMay 30, 2017
Grant dateMay 30, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a wiring structure, comprising: forming an insulating interlayer on a substrate, the insulating interlayer including an opening and pores distributed therein and exposed at a surface thereof; forming a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening by exposing the insulating interlayer to a silane compound represented by the formula: (Re)a(Si)(R)b(Bu)c, wherein Re, R and Bu represent a reactive group, an alkyl group and a sealing group, respectively, bonded to a silicon (Si) atom, wherein Re is an amino group, a halogen, a hydroxyl group or an alkoxy group, R is a C 1 -C 3 alkyl group, and Bu is a C 4 -C 10 branched alkyl group or a C 4 -C 10 unsaturated alkyl group, and wherein each of a, b and c is 1 or 2, and a sum of a, b and c is 4; and forming a conductive pattern filling the opening on the pore sealing layer. 2. The method of claim 1 , wherein the reactive group is the amino group. 3. The method of claim 2 , wherein the reactive group is at least one selected from the group consisting of dimethyl amino (—N(CH 3 ) 2 ), methyl ethyl amino (—N(CH 3 )(CH 2 CH 3 )) and diethyl amino (—N(CH 2 CH 3 ) 2 ). 4. The method of claim 1 , wherein the sealing group is a C 4 -C 6 branched alkyl group or a C 4 -C 6 unsaturated alkyl group. 5. The method of claim 4 , wherein the sealing group is a tert-butyl group or a butenyl group. 6. The method of claim 1 , wherein the alkyl group is a methyl or an ethyl. 7. The method of claim 1 , wherein a is 1, b is 2, and c is 1. 8. The method of claim 1 , wherein the pore sealing layer selectively caps pores exposed at the surface of the insulating interlayer relative to pores distributed within the insulating interlayer. 9. The method of claim 1 , wherein the insulating interlayer includes a hydroxyl group exposed at the surface thereof, and wherein exposing the insulating interlayer to the silane compound includes reacting the hydroxyl group with the reactive group of the silane compound. 10. The method of claim 9 , wherein reacting the hydroxyl group with the reactive group of the silane compound includes subjecting the insulating interlayer to at least one selected from the group consisting of an ultraviolet (UV) irradiation, an infrared (IR) irradiation and a plasma treatment. 11. The method of claim 1 , wherein forming the conductive pattern includes forming a barrier layer in contact with the pore sealing layer. 12. The method of claim 11 , wherein forming the conductive pattern further includes: forming a seed layer partially filling the opening on the barrier layer; and forming a metal layer filling a remaining portion of the opening on the seed layer by a plating process. 13. The method of claim 1 , further comprising, before forming the insulating interlayer, forming a lower structure on the substrate, the lower structure including a lower wiring, wherein a top surface of the lower wiring is exposed through the opening. 14. The method of claim 1 , wherein forming the insulating interlayer including the opening and pores comprises subjecting the insulating interlayer to a modification treatment to create the pores. 15. The method of claim 14 , wherein the modification treatment includes at least one selected from the group consisting of a UV irradiation and a plasma treatment. 16. A method of forming a wiring structure, comprising: forming a lower structure including a lower wiring on a substrate; forming an insulating interlayer having pores on the lower structure; etching the insulating interlayer to form an opening through which the lower wiring is exposed; forming an intermediate layer capping the pores on a surface of the insulating interlayer and a sidewall of the opening by exposing the insulating interlayer to a silane compound represented by the formula: (Re)(Si)(R) 2 (Bu), wherein Re, R and Bu represent a reactive group, an alkyl group and a sealing group, respectively, bonded to a silicon (Si) atom, and wherein Re is an amino group, R is a C 1 -C 3 alkyl group, and Bu is a C 4 -C 10 branched alkyl group or a C 4 -C 10 unsaturated alkyl group, and forming a conductive pattern filling the opening on the intermediate layer. 17. The method of claim 16 , wherein the intermediate layer is not formed on a bottom of the opening. 18. The method of claim 17 , wherein forming the conductive pattern includes forming a barrier layer in contact with the intermediate layer and a top surface of the lower wiring. 19. A method of manufacturing a semiconductor device, comprising: forming a plurality of semiconductor fins on a substrate; forming a gate structure extending on and crossing the semiconductor fins; forming source/drain regions at upper portions of the semiconductor fins adjacent to the gate structure; forming a contact electrically connected to at least one of the source/drain regions; forming an insulating interlayer on the gate structure, the source/drain regions and the contact, the insulating interlayer including an opening therein; forming an intermediate layer on a surface of the insulating interlayer and a sidewall of the opening by exposing the insulating interlayer to a silane compound represented by the formula: (Re)a(Si)(R)b(Bu)c, wherein Re, R and Bu represent a reactive group, an alkyl group and a sealing group, respectively, bonded to a silicon (Si) atom, wherein Re is an amino group, a halogen, a hydroxyl group or an alkoxy group, R is a C 1 -C 3 alkyl group, Bu is a C 4 -C 10 branched alkyl group or a C 4 -C 10 unsaturated alkyl group, and wherein each of a, b and c is 1 or 2, and a sum of a, b and c is 4; and forming a conductive pattern on the intermediate layer and filling the opening. 20. The method of claim 19 , wherein the silane compound includes at least one compound selected from the group consisting of the compounds represented by Chemical Formulae (1) to (10):

Assignees

Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • of dielectric parts comprising air gaps · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • by contacting with gases, liquids or plasmas · CPC title

  • by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

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What does patent US9666478B2 cover?
In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern fillin…
Who is the assignee on this patent?
Oszinda Thomas, Yim Tae-Jin, Ahn Sang-Hoon, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10W20/076. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 30 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).