Method of making multi-layer electronic components with plated terminations

Patent metadata

Field	Value
Publication number	US-9666366-B2
Application number	US-95197204-A
Country	US
Kind code	B2
Filing date	Sep 28, 2004
Priority date	Apr 15, 2002
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrodes and optional anchor tabs, such as via electroless and/or electrochemical processes, until exposed portions of selected groups thereof are connected.

First claim

What is claimed:

1. A method of making a multi-layer electronic component, comprising the steps of:
providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges;
interleaving a plurality of electrodes between selected of said plurality of insulating substrates;
exposing selected portions of said electrodes along at least one edge of said substrates;
providing anchor tabs interleaved at selected locations between the insulating substrates and positioned such that they are not in direct contact with any of said plurality of electrodes;
exposing portions of said anchor tabs at selected edges of the insulating substrates; and
submersing the electronic component in a plating solution to deposit at least one layer of termination material directly on said exposed portions of said electrodes and on said exposed portions of said anchor tabs until the exposed portions of selected of said electrodes and anchor tabs are connected by the at least one layer of termination material;
wherein the step of plating is performed using an electroless process;
the electroless process comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer; and
the method further comprises the step of covering the copper termination layer with a resistive layer.

2. The method of claim 1 , wherein the electroless process is followed by an electrochemical process.

3. The method of claim 1 , further comprising plating the resistive layer with a conductive layer.

4. A method of making a multi-layer electronic component, comprising the steps of:
providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges;
interleaving a plurality of electrodes between selected of said plurality of insulating substrates;
exposing selected portions of said electrodes along at least one edge of said substrates;
providing anchor tabs interleaved at selected locations between the insulating substrates and positioned such that they are not in direct contact with any of said plurality of electrodes;
exposing portions of said anchor tabs at selected edges of the insulating substrates;
submersing the electronic component in a copper plating solution to deposit at least one layer of copper termination material directly on said exposed portions of said electrodes and on said exposed portions of said anchor tabs until the exposed portions of selected of said electrodes and anchor tabs are connected by the at least one layer of copper termination material; and
covering the copper termination layer with a resistive layer.

5. The method of claim 4 , further comprising plating the resistive layer with a conductive layer.

6. The method of claim 4 , wherein the step of plating is performed using an electroless process followed by an electrochemical process.

7. The method of claim 4 , wherein the step of plating is performed using an electroless process.

Assignees

• Ritter Andrew P
• Heistand Ii Robert
• Galvagni John L
• Dattaguru Sriram
• Avx Corp

Inventors

• Ritter Andrew P
• Heistand Ii Robert
• Galvagni John L
• Dattaguru Sriram

Classifications

• H01C1/14

  Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors · CPC title

• C23C18/48

  Coating with alloys · CPC title

• Y10T29/49099

  Coating resistive material on a base · CPC title

• H05K2201/09709

  Staggered pads, lands or terminals; Parallel conductors in different planes · CPC title

• C23C18/32

  Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence) · CPC title