Semiconductor device having hierarchically structured bit lines

Patent metadata

Field	Value
Publication number	US-9666306-B2
Application number	US-201614992645-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Aug 14, 2012
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

First claim

What is claimed is:

1. A method for accessing a semiconductor memory device having hierarchically structured bit lines comprising:
receiving address information;
determining whether the address information corresponds to stored defective address information; and
if the address information does not correspond to the stored defective address information:
activating a first word line corresponding to the address information in a first memory mat,
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in the first memory mat, and
activating a plurality of sense amplifiers connected to the global bit lines in the first memory mat;
if the address information corresponds to the stored defective address information:
activating a redundant word line in a second memory mat,
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in the second memory mat, and
activating a plurality of sense amplifiers connected to the global bit lines in the second memory mat.

2. The method as claimed in claim 1 wherein the defective address information is stored in fuses.

3. The method as claimed in claim 1 wherein the first word line and the redundant word line are a first sub-word line and a redundant sub-word line.

4. The method as claimed in claim 1 wherein the first memory mat does not include a redundant word line.

5. The method as claimed in claim 1 wherein the first and second memory mats have an open bit line structure.

6. The method as claimed in claim 1 wherein a pair of global bit lines is connected to each sense amplifier.

7. The method as claimed in claim 6 wherein a first global bit line of the pair of global bit lines is located in the first and second memory mats and a second global bit line of the pair of global bit lines is located in memory mats adjacent to the first and second memory mats.

8. The method as claimed in claim 1 wherein the semiconductor memory device is a DRAM.

9. The method as claimed in claim 1 further comprising:
if the address information does not correspond to the stored defective address information:
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in a third memory mat adjacent to the first memory mat, and
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in a fourth memory mat adjacent to the first memory mat and opposite the third memory mat; and
if the address information corresponds to the stored defective address information:
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in a fifth memory mat adjacent to the second memory mat, and
activating a plurality of local switches to connect a plurality of local bit lines to a plurality of global bit lines in a sixth memory mat adjacent to the second memory mat and opposite the fifth memory mat.

10. The method as claimed in claim 9 wherein the local switches in the third and fourth memory mats are located symmetrically with respect to the sense amplifiers connected to the global bit lines in the first memory mat and the local switches in the fifth and sixth memory mats are located symmetrically with respect to the sense amplifiers connected to the global bit lines in the second memory mat.

Assignees

• Ps4 Luxco S A R I
• Longitude Semiconductor Sarl

Inventors

• Mochida Noriaki

Classifications

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C29/808 Primary

  using a flexible replacement scheme · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title