Semiconductor device having hierarchically structured bit lines

Patent metadata

Field	Value
Publication number	US-9236149-B2
Application number	US-201313964782-A
Country	US
Kind code	B2
Filing date	Aug 12, 2013
Priority date	Aug 14, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

First claim

What is claimed is:

1. A device comprising:
a first memory mat including:
a plurality of first memory cells;
a defective memory cell;
a first global bit line;
a plurality of first local bit lines coupled in common to the first global bit line, each of the first local bit lines coupled to associated ones of the first memory cells, one of the first local bit lines being further coupled to the defective memory cell; and
a plurality of first transistors each coupled between an associated one of the first local bit lines and the first global bit line;
a second memory mat including:
a plurality of second memory cells;
a redundant memory cell;
a second global bit line;
a plurality of second local bit lines coupled in common to the second global bit line, each of the second local bit lines coupled to associated ones of the second memory cells, one of the second local bit lines being further coupled to the redundant memory cell; and
a plurality of second transistors each coupled between an associated one of the second local bit lines and the second global bit line, wherein one of the second transistors is coupled between the one of the second local bit lines and the second global bit line;
a plurality of terminals receiving access address information; and
a control circuit including a storing unit that is configured to store defective address information that designate the defective memory cell of the first memory mat and accessing unit that is configured to access to the redundant memory cell of the second memory mat when the access address information coincides with the defective address information, wherein the accessing unit of the control circuit is configured to render the one of the second transistors conductive when the access address information coincides with the defective address information.

2. The device as claimed in claim 1 , further comprising;
a third memory mat including:
a plurality of third memory cells;
a third global bit line; and
a plurality of third local bit lines coupled in common to the third global bit line, each of the third local bit lines being coupled to associated ones of the third memory cells;
a fourth memory mat including:
a plurality of fourth memory cells;
a fourth global bit line; and
a plurality of fourth local bit lines coupled in common to the fourth global bit line, each of the fourth local bit lines being coupled to associated ones of the fourth memory cells;
a first sense amplifier arranged between the first and third memory mats and coupled between the first and third global bit lines; and
a second sense amplifier arranged between the second and fourth memory mats and coupled between the second and fourth global bit lines.

3. The device as claimed in claim 2 , wherein each of the first, second, third and fourth global bit lines extends in a first direction, and the first, second, third and fourth memory mats and the first and second sense amplifiers are arranged in the first direction.

4. The device as claimed in claim 2 , wherein the third memory mat further includes a plurality of third transistors each coupled between an associated one of the third local bit lines and the third global bit line, the fourth memory mat further includes a plurality of fourth transistors each coupled between an associated one of the fourth local bit lines and the fourth global bit line, and the accessing unit of the control circuit is configured to render the one of the second transistors and one of the fourth transistors conductive when the access address information coincides with the defective address information.

5. The device as claimed in claim 4 , wherein the one of the second transistors and the one of the fourth transistors are located substantially symmetrically against the second sense amplifier to each other.

6. The device as claimed in claim 2 , wherein the first, second, third and fourth memory mats are open bit line structure.

7. A device comprising:
first, second, third and fourth global bit lines;
a first sense amplifier that amplifies a potential difference between the first and fourth global bit lines;
a second sense amplifier that amplifies a potential difference between the second and third global bit lines;
a plurality of first local bit lines;
a plurality of second local bit lines;
a plurality of third local bit lines;
a plurality of fourth local bit lines;
a plurality of first hierarchy switches each connected between the first global bit line and an associated one of the first local bit lines;
a plurality of second hierarchy switches each connected between the second global bit line and an associated one of the second local bit lines;
a plurality of third hierarchy switches each connected between the third global bit line and an associated one of the third local bit lines;
a plurality of fourth hierarchy switches each connected between the fourth global bit line and an associated one of the fourth local bit lines;
a plurality of first word lines each intersecting with an associated one of the first local bit lines, the first word lines including a defective word line;
a plurality of second word lines each intersecting with an associated one of the second local bit lines, the second word lines including a redundant word line;
a plurality of third word lines each intersecting with an associated one of the third local bit lines;
a plurality of fourth word lines each intersecting with an associated one of the fourth local bit lines;
a plurality of first memory cells each arranged at an associated one of intersections of the first word lines and the first local bit lines;
a plurality of second memory cells each arranged at an associated one of intersections of the second word lines and the second local bit lines;
a plurality of third memory cells each arranged at an associated one of intersections of the third word lines and the third local bit lines;
a plurality of fourth memory cells each arranged at an associated one of intersections of the fourth word lines and the fourth local bit lines; and
a control circuit that activates the redundant word line, brings one of the second hierarchy switches that is connected to one of the second local bit lines intersecting with the redundant word line into conductive state, and further activates the second sense amplifier, in response to an access request to the defective word line.

8. The device as claimed in claim 7 , wherein, in response to an access request a normal word line having no defect among the first word lines, the control circuit activates the normal word line, brings one of the first hierarchy switches that is connected to one of the first local bit lines intersecting with the normal word line into conductive state, and further activates the first sense amplifier.

9. The device as claimed in claim 8 , wherein, in response to the access request to the normal word line, the control circuit further brings one of the fourth hierarchy switches that is located symmetrically to the first hierarchy switch to be brought into conductive state with respect to the first sense amplifier into conductive state.

10. The device as claimed in claim 9 , wherein, in response to the access request to the normal word line, the control circuit deactivates one of the fourth word lines intersecting with one of the fourth local bit lines connected to the fourth hierarchy switch to be brought into conductive state.

11. The device as claimed in claim 7 , wherein, in response to the access request to the defective word line, the control circuit further brings one of the third hierarchy switches that is located symmetrically to the second hierarchy switch to be brought into con

Assignees

• Ps4 Luxco Sarl

Inventors

• Mochida Noriaki

Classifications

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C29/808 Primary

  using a flexible replacement scheme · CPC title