Method and program for designing integrated circuit

Patent metadata

Field	Value
Publication number	US-9665678-B2
Application number	US-201514744178-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jul 29, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

First claim

What is claimed is:

1. A method of designing an integrated circuit (IC), comprising:
a processor receiving input data defining an IC with a plurality of first standard cells, the first standard cells having first footprints and pinouts and physical attributes that result in first yield and performance characteristics;
the processor preparing at least one second standard cell having the same, first, footprint and pinout and as a corresponding one of the first standard cells and having a layout including physical features that provide different yield or performance characteristics of the IC than a corresponding one of the plurality of first standard cells;
the processor swapping at least one of the first standard cells included in the IC for the corresponding second standard cell; and
the processor generating output data defining the IC including the second standard cell,
wherein the first and second standard cells have the same function, and
wherein the swapping of the at least one of the first standard cells for the corresponding second standard cell comprises swapping a first standard cell that is not connected to a critical path of the IC according to the input data for the second standard cell.

2. The method of claim 1 , wherein the swapping of the at least one of the first standard cells for the corresponding second standard cell further comprises re-swapping the second standard cell for the corresponding first standard cell, based on a result of analysis of the critical path of the IC including the second standard cell.

3. The method of claim 1 , wherein the swapping of the at least one of the first standard cells for the corresponding second standard cell further comprises re-swapping the second standard cell for the corresponding first standard cell, based on a result of analysis of power consumption of the IC including the second standard cell.

4. The method of claim 1 , wherein the input data comprises netlist data of the IC that is synthesized with the plurality of first standard cells.

5. The method of claim 1 , wherein the input data comprises layout data of the IC, which is generated by placing and routing the plurality of first standard cells.

6. The method of claim 1 , wherein the first standard cell comprises an active region including at least one stepwise portion, and
the second standard cell comprises an active region from which the stepwise portion is removed.

7. The method of claim 6 , wherein the active region of the first standard cell comprises at least one discontinuous portion removed by using an etching process, and
the second standard cell comprises the active region from which the stepwise portion is removed by expanding or reducing even the at least one discontinuous portion of the active region of the first standard cell.

8. A method of designing an integrated circuit (IC), comprising:
preparing a first library including information corresponding to a plurality of first standard cells having first footprints and pinouts and layouts having physical attributes that result in first yield and performance characteristics and a second library including information corresponding to at least one second standard cell having a layout with the same footprint and pinout as a corresponding one of the first standard cells and physical attribute that provides different yield or performance characteristics of the IC than a corresponding first standard cell;
defining the IC based on the first and second libraries;
a processor swapping at least one of the first standard cells included in the IC for the corresponding second standard cell; and
the processor generating output data defining the IC including the first and second standard cells,
wherein the swapping of the at least one of the first standard cells for the corresponding second standard cell comprises swapping a first standard cell, which is not connected to a critical path of the IC defined based on the first library, for the second standard cell.

9. The method of claim 8 , wherein the swapping of the at least one of the first standard cells further comprises re-swapping the second standard cell for the corresponding first standard cell, based on a result of analysis of the critical path of the IC including the second standard cell.

10. The method of claim 8 , wherein the defining of the IC based on the first and second libraries comprises generating netlist data by synthesizing the IC with the plurality of first and second standard cells.

11. The method of claim 8 , wherein the defining of the IC based on the first and second libraries comprises generating layout data of the IC in which the plurality of first and second standard cells are placed and routed.

12. The method of claim 8 , wherein the first standard cell comprises an active region including at least one stepwise portion, and
the second standard cell comprises an active region from which the stepwise portion is removed.

13. The method of claim 12 , wherein the active region of the first standard cell comprises at least one discontinuous portion that is removed by using an etching process, and
the second standard cell comprises an active region, from which the stepwise portion is removed by expanding or reducing even the at least one discontinuous portion of the active region of the first standard cell.

14. A method of designing an integrated circuit, comprising:
a processor receiving input data initially-defining an integrated circuit using a plurality of first standard cells designed to include physical features that optimize a performance or yield characteristic, wherein each first standard cell has a first footprint and pinout;
the processor substituting at least one second standard cell designed to include physical features that optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells, wherein each second standard cell has the same, first, footprint and pinout as a corresponding first standard cell; and
the processor generating output data defining the integrated circuit including the second standard cell, wherein the first and second corresponding standard cells have the same function, wherein:
the input data comprises layout data of the integrated circuit, which is generated by placing and routing the plurality of first standard cells;
the substituting the corresponding second standard cell for at least one of the first standard cells comprises substituting for a first standard cell that is not connected to a critical path of the IC according to the input data for the second standard cell; and
the first standard cell comprises an active region including at least one stepwise portion, and the second standard cell comprises an active region from which the stepwise portion is removed.

15. The method of claim 14 , wherein the first standard cells are optimized for the performance characteristic of processing speed and the second standard cell is optimized for production yield.

16. The method of claim 14 , wherein the first standard cells are optimized for the performance characteristic of power consumption and the second standard cells is optimized for production yield.

17. The method of claim 14 , wherein the first standard cells are optimized for production yield and the second standard cells are optimized for a performance characteristic.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Sung-We
• Lee Dal-Hee
• Kim Ha-Young
• Seo Jae-Woo
• Kim Jin-Tae

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/505

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title