Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)

Patent metadata

Field	Value
Publication number	US-9663353-B2
Application number	US-201314403571-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2013
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package assembly comprising:
an application-specific integrated circuit (ASIC) having an active side and an inactive side opposite the active side;
a microelectromechanical system (MEMS) having an active side and an inactive side; and
one or more interconnects;
wherein the MEMS is coupled directly to the ASIC through the one or more interconnects; and
wherein the MEMS, the ASIC, and the one or more interconnects form a cavity between the MEMS, the ASIC, and the one or more interconnects such that a face of the MEMS is exposed within the cavity.

2. The package assembly of claim 1 , wherein the MEMS is a first MEMS, the cavity is a first cavity, and the one or more interconnects are first one or more interconnects, the package assembly further comprising:
a second MEMS; and
a second one or more interconnects;
wherein the second MEMS is coupled directly to the ASIC through the second one or more interconnects, wherein the second MEMS, the ASIC, and the second one or more interconnects form a second cavity between the second MEMS, the ASIC, and the second one or more interconnects.

3. The package assembly of claim 2 , wherein the first MEMS is a gyroscope, an accelerometer, a magnetometer, a microphone, a filter, an oscillator, a pressure sensor, a radio frequency identification (RFID) chip, or a speaker.

4. The package assembly of claim 2 , further comprising one or more package-level interconnects coupled with the ASIC.

5. The package assembly of claim 4 , wherein an individual package-level interconnect of the one or more package-level interconnects is coupled with the inactive side of the first MEMS; and
wherein the individual package-level interconnect is coupled with the ASIC through a through silicon via (TSV) from the inactive side of the MEMS to the active side of the MEMS, wherein the TSV is coupled with the ASIC.

6. The package assembly of claim 2 , wherein an interconnect of the first one or more interconnects is coupled with a redistribution layer (RDL) of the ASIC.

7. The package assembly of claim 6 , wherein the first one or more interconnects and the ASIC are coupled with an underfill;
wherein the underfill is configured to hermetically seal the first cavity; and
wherein the first cavity is substantially free of the underfill.

8. The package assembly of claim 7 , wherein the RDL is coupled with each of the first one or more interconnects and the underfill, the RDL configured to further hermetically seal the first cavity.

9. The package assembly of claim 7 , further comprising a mold compound encapsulating at least the inactive side of the first MEMS, the underfill, and at least a portion of the ASIC, wherein the cavity is substantially free of the mold compound.

10. The package assembly of claim 2 , further comprising a mold compound covering at least a portion of one of the active side or inactive side of the ASIC, wherein the first MEMS is coupled with the other one of the active side or the inactive side of the ASIC.

11. The package assembly of claim 2 , wherein the ASIC comprises a third cavity disposed in the active side or the inactive side of the ASIC; and
wherein the first MEMS is coupled with the ASIC within the third cavity.

12. The package assembly of claim 2 , wherein the first MEMS is coupled to one of the active side or the inactive side of the ASIC through the first one or more interconnects; and
wherein the first MEMS is electrically coupled to the other one of the active side or the inactive side of the ASIC through one or more through silicon vias (TSVs) in the ASIC, wherein the one or more TSVs are configured to provide an electrical pathway from the one of the active side or the inactive side of the ASIC to the other one of the active side or the inactive side of the ASIC.

13. The package assembly of claim 12 , wherein the first MEMS is electrically coupled to one or more of the TSVs via one or more wirebonds.

14. A system comprising:
a circuit board;
a package assembly coupled with the circuit board, the package assembly comprising:
an application-specific integrated circuit (ASIC) having an active side and an inactive side opposite the active side;
a microelectromechanical system (MEMS) having an active side and an inactive side; and
one or more interconnects;
wherein the MEMS is coupled directly to the ASIC through the one or more interconnects; and
wherein the MEMS, the ASIC, and the one or more interconnects form a cavity between the MEMS, the ASIC, and the one or more interconnects, wherein the cavity defines a space between an exposed face of the MEMS and the ASIC.

15. The system of claim 14 , wherein the MEMS is a first MEMS, the cavity is a first cavity, and the one or more interconnects are first one or more interconnects, the package assembly further comprising:
a second MEMS; and
a second one or more interconnects;
wherein the second MEMS is coupled directly to the ASIC through the second one or more interconnects, wherein the second MEMS, the ASIC, and the second one or more interconnects form a second cavity between the second MEMS, the ASIC, and the second one or more interconnects.

16. The system of claim 15 , wherein the first MEMS is a gyroscope, an accelerometer, a magnetometer, a microphone, a filter, an oscillator, a pressure sensor, a radio frequency identification (RFID) chip, or a speaker.

Assignees

• Intel Ip Corp

Inventors

• Ofner Gerald
• Meyer Thorsten
• Mahnkopf Reinhard
• Geissler Christian
• Augustin Andreas

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• B81C1/00238 Primary

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81B7/02

  containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title

• B81C1/0023 Primary

  Packaging together an electronic processing unit die and a micromechanical structure die (MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261) · CPC title