Semiconductor device

Patent metadata

Field	Value
Publication number	US-9660356-B1
Application number	US-201615282240-A
Country	US
Kind code	B1
Filing date	Sep 30, 2016
Priority date	Nov 25, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

In a semiconductor device, a plurality of semiconductor units is electrically connected in parallel using a connecting device. The connecting device includes a first connecting unit and a second connecting unit. The first connecting unit is electrically connected to a control terminal of each semiconductor unit. The second connecting unit is electrically connected to a main terminal of each semiconductor unit.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of semiconductor units; and
a connecting device which electrically connects the semiconductor units in parallel,
wherein each of the semiconductor units includes:
a laminated substrate which has an insulating board and a circuit board arranged on a front surface of the insulating board;
a plurality of semiconductor elements each having a rear surface fixed to the circuit board and a front surface having a main electrode and a control electrode;
a wiring member electrically connected to the main electrode and the control electrode of the semiconductor element;
a control terminal electrically connected to the control electrode of the semiconductor element via the wiring member; and
a main terminal electrically connected to the main electrode of the semiconductor element via the wiring member,

wherein, inside each respective semiconductor unit, the laminated substrate, the semiconductor element, and the wiring member constitute a respective three-level inverter circuit, and
wherein the connecting device includes:
a first connecting unit electrically connected to the control terminal of each of the plurality of semiconductor units, and
a second connecting unit electrically connected to the main terminals of each of the plurality of semiconductor units.

2. The semiconductor device according to claim 1 , wherein the wiring member of each semiconductor unit includes:
a printed circuit board arranged facing a principal surface of the insulating board of the laminated substrate, and
a plurality of conductive posts which electrically connects the printed circuit board and the semiconductor elements.

3. The semiconductor device according to claim 2 , wherein the main terminal of each semiconductor unit includes a P terminal, an N terminal, an M terminal, and a U terminal, and
wherein at least the P terminal, the N terminal and the M terminal among the main terminals are provided in a center part of the respective semiconductor unit.

4. The semiconductor device according to claim 1 , wherein the second connecting unit is stacked on the first connecting unit of the connecting device.

5. The semiconductor device according to claim 4 , wherein the main terminal of each of the semiconductor units penetrates the first connecting unit, and
wherein the second connecting unit is stacked on the first connecting unit and is electrically connected to the main terminal of each of the semiconductor units penetrating through the first connecting unit.

6. The semiconductor device according to claim 1 , wherein a wiring of the second connecting unit is configured such that a length from the main terminal of each of the semiconductor units to a single U terminal of the second connecting unit is substantially equal.

7. The semiconductor device according to claim 1 , wherein a wiring of the second connecting unit is configured such that a length from the main terminal of each of the semiconductor units to a single U terminal of the second connecting unit has a nearly equal inductance.

8. The semiconductor device according to claim 1 , wherein the second connecting unit includes a first wiring plate and a second wiring plate.

9. The semiconductor device according to claim 8 , the first wiring plate is symmetrical with respect to a center line of the first wiring plate.

10. The semiconductor device according to claim 8 ,
wherein the second connecting unit includes an external terminal that is electrically connected to the first wiring plate or the second wiring plate and to the main terminal of each of the plurality of semiconductor units via the first wiring plate or second wiring plate, and
wherein the external terminal is located in a vicinity of a center part of the second connecting unit.

11. The semiconductor device according to claim 1 ,
wherein the second connecting unit includes an insulating board, a first wiring plate arranged on a front surface of the insulating board, and a second wiring plate arranged on a rear surface of the insulating board.

12. The semiconductor device according to claim 11 ,
the second wiring plate is arranged on the rear surface of the insulating board so as to overlap with the first wiring plate.

13. The semiconductor device according to claim 12 ,
wherein the main terminal is arranged outside the external terminal.

Assignees

• Fuji Electric Co Ltd

Inventors

• Nakamura Hideyo

Classifications

• H01R12/58

  terminals for insertion into holes · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title