Thin film transistor and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9660103-B2
Application number	US-201414888213-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Jun 28, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiO x film having a hydrogen concentration of 3.5 atomic % or lower.

First claim

The invention claimed is:

1. A thin film transistor comprising, in order;
a gate electrode,
a gate insulator film,
an oxide semiconductor layer,
a source-drain electrode, and
a passivation film comprising more than one layer on a substrate,
wherein
the oxide semiconductor layer comprises O, Sn, In, Ga, and Zn wherein the amount of In, Ga, Zn, and Sn relative to the total amount of In, Ga, Zn, and Sn is:
15 atomic %≦In≦25 atomic %,
5 atomic %≦Ga≦20 atomic %,
40 atomic %≦Zn≦60 atomic %, and
9 atomic %≦Sn≦25 atomic %;
the passivation film comprises a first protective film in contact to the oxide semiconductor layer and a second protective film comprising one or more layers other than the first protective film;
the first protective film is a SiO x film; and
the hydrogen concentration in the first protective film is 3.5 atomic % or lower.

2. The thin film transistor of claim 1 , wherein
the second protective film is an insulating compound film or a laminate film comprising a resin film and the insulating compound film.

3. The thin film transistor of claim 2 , wherein
the insulating compound film is an oxide, a nitride, or an oxynitride film comprising one or more elements selected from the group consisting of Si, Al, Ti, Ta, Ce, Ga, Hf, Nb, V, W, Y, and Zr.

4. The thin film transistor of claim 3 , wherein
the insulating compound film comprises SiN x film and an oxide film comprising one or more elements selected from the group consisting of Si, Al, Ti, Ta, Ce, Nb, V, W, Y, and Zr.

5. The thin film transistor of claim 2 , wherein
the thickness of the first protective film is larger than or equal to 30 nm.

6. The thin film transistor of claim 1 , wherein the amount of In relative to the total amount of In, Ga, Zn, and Sn is 16 atomic % to 23 atomic %.

7. The thin film transistor of claim 1 , wherein the amount of Ga relative to the total amount of In, Ga, Zn, and Sn is 10 atomic % to 19 atomic %.

8. The thin film transistor of claim 1 , wherein the amount of Zn relative to the total amount of in, Ga, Zn, and Sn is 43 atomic % to 60 atomic %.

9. The thin film transistor claim 1 , wherein the amount of Zn relative to the total amount of In, Ga, Zn, and Sn is 43 atomic % to 50 atomic %.

10. The thin film transistor of claim 1 , wherein
the specific resistance of the oxide semiconductor layer is 2.1×10 2 Ω-cm or larger and 1.0×10 5 Ω-cm or smaller.

11. The thin film transistor of claim 1 , wherein
the oxide semiconductor layer comprises Sn in an amount of 15 atomic % to 25 atomic % relative to the total amount of metal elements in the oxide semiconductor layer.

12. The thin film transistor of claim 1 , wherein
the amount of In, Ga, Zn, and Sn relative to the total amount of In, Ga, Zn, and Sn is:
16 atomic %≦In≦23 atomic %,
10 atomic %≦Ga≦19 atomic %,
43 atomic %≦Zn≦60 atomic %, and
15 atomic %≦Sn≦25 atomic %.

13. The thin film transistor of claim 1 , wherein
the thickness of the first protective film is larger than or equal to 30 nm.

14. The thin film transistor as set forth in claim 1 wherein
the source-drain electrode comprises a pure Mo film, a Mo alloy film, or both.

15. The thin film transistor of claim 1 , wherein the source-drain electrode is a laminate film comprising;
one or more films selected from a pure Mo film and a Mo alloy film, and are in direct contact to the oxide semiconductor layer; and
one or more films selected from the group consisting of a pure Al film, a pure Cu film, an Al alloy film, and a Cu alloy film.

16. Method of manufacturing the thin film transistor of claim 1 comprising:
forming the gate electrode on the substrate;
forming the gate insulator film on the gate electrode;
forming the oxide semiconductor layer on the gate insulator film wherein the oxide semiconductor layer comprises O, Sn, In, Ga and Zn, the amounts of In, Ga, Zn, and Sn relative to the total amount of In, Ga, Zn, and Sn are: 15 atomic %≦In ≦25 atomic %, 5 atomic %≦Ga ≦20 atomic %, 40 atomic %≦Zn≦60 atomic %, and 9 atomic %≦Sn≦25 atomic %;
forming the source-drain electrode on the oxide semiconductor layer comprising carrying out patterning of the source-drain electrode with an acid-based etchant; and
forming the passivation film on the source-drain electrode wherein the passivation film comprises the first protective film in contact to the oxide semiconductor layer and the second protective film comprising one or more layers other than the first protective film, the first protective film is the SiO x film and the hydrogen concentration in the first protective film is 3.5 atomic % or lower, wherein forming the passivation film comprises carrying out an oxidation treatment after forming the SiO x as the first protective film and forming the second protective film on the first protective film.

17. The method of claim 16 , wherein
the oxidation treatment is a heat treatment conducted at a temperature of higher than or equal to 130° C. and lower than or equal to 400° C.

18. The method of claim 16 further comprising;
carrying out a heat treatment after the forming of the second protective film.

19. The method of claim 17 , further comprising:
carrying out a heat treatment after the forming of the second protective film.

Assignees

• Kobe Steel Ltd
• Kobe Steel Ltd

Inventors

• Ochi Mototaka
• Morita Shinya
• Takanashi Yasuyuki
• Goto Hiroshi
• Kugimiya Toshihiro

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H01L27/1222

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L27/1214

  Electricity · mapped topic