Semiconductor device comprising an oxide semiconductor layer

US9660101B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9660101-B2
Application numberUS-201615165305-A
CountryUS
Kind codeB2
Filing dateMay 26, 2016
Priority dateNov 16, 2012
Publication dateMay 23, 2017
Grant dateMay 23, 2017

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: an oxide semiconductor layer over a substrate; a first oxide layer over the oxide semiconductor layer; a source electrode and a drain electrode over the first oxide layer; and a second oxide layer in contact with the source electrode and the drain electrode, wherein the first oxide layer and the second oxide layer are in contact with each other, wherein the first oxide layer and the second oxide layer comprise at least one metal element contained in the oxide semiconductor layer, and wherein energy at a bottom of a conduction band of the first oxide layer is smaller than that of the oxide semiconductor layer. 2. The semiconductor device according to claim 1 , wherein the one metal element is indium. 3. The semiconductor device according to claim 1 , further comprising a third oxide layer between the substrate and the oxide semiconductor layer, wherein the third oxide layer is in contact with the oxide semiconductor layer. 4. The semiconductor device according to claim 1 , wherein energy at a bottom of a conduction band of the second oxide layer is smaller than that of the oxide semiconductor layer. 5. The semiconductor device according to claim 1 , wherein energy at a bottom of a conduction band of the second oxide layer is smaller than that of the first oxide layer. 6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises crystals which are aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer. 8. A semiconductor device comprising: an oxide semiconductor layer over a substrate; a first oxide layer over the oxide semiconductor layer; a source electrode and a drain electrode over the first oxide layer; a second oxide layer in contact with the source electrode and the drain electrode; a gate insulating layer over the second oxide layer; and a gate electrode over the gate insulating layer, wherein the first oxide layer and the second oxide layer are in contact with each other, wherein the first oxide layer and the second oxide layer comprise at least one metal element contained in the oxide semiconductor layer, and wherein energy at a bottom of a conduction band of the first oxide layer is smaller than that of the oxide semiconductor layer. 9. The semiconductor device according to claim 8 , wherein the one metal element is indium. 10. The semiconductor device according to claim 8 , further comprising a third oxide layer between the substrate and the oxide semiconductor layer, wherein the third oxide layer is in contact with the oxide semiconductor layer. 11. The semiconductor device according to claim 8 , wherein energy at a bottom of a conduction band of the second oxide layer is smaller than that of the oxide semiconductor layer. 12. The semiconductor device according to claim 8 , wherein energy at a bottom of a conduction band of the second oxide layer is smaller than that of the first oxide layer. 13. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 14. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises crystals which are aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer. 15. A semiconductor device comprising: a first oxide layer; an oxide semiconductor layer over the first oxide layer; a second oxide layer over the oxide semiconductor layer; a third oxide layer over the second oxide layer, wherein the second oxide layer and the third oxide layer comprise at least one metal element contained in the oxide semiconductor layer, wherein energy at a bottom of a conduction band of the second oxide layer is smaller than energy at a bottom of a conduction band of the oxide semiconductor layer, and wherein energy at a bottom of a conduction band of the third oxide layer is smaller than that of the second oxide layer. 16. The semiconductor device according to claim 15 , wherein the one metal element is indium. 17. The semiconductor device according to claim 15 , wherein the first oxide layer is provided over a substrate. 18. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 19. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer comprises crystals which are aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

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What does patent US9660101B2 cover?
Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it i…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L29/7869. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 23 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).