Semiconductor device and method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9659948-B2
Application number	US-201514856577-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Sep 17, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region;
a logic gate stack disposed in the logic region, wherein the logic gate stack has a first top surface;
a non-volatile gate stack disposed in the recess, wherein the non-volatile gate stack has a second top surface and the second top surface is lower than the first top surface by a step height; and
an inter-layer dielectric (ILD) layer disposed on the substrate to cover the second top surface of the non-volatile gate stack, wherein the ILD layer has a third top surface coplanar with the first top surface and higher than the second top surface by the step height.

2. The semiconductor device according to claim 1 , wherein the non-volatile gate stack includes an oxide-nitride-oxide (ONO) stack-layer between an upper polysilicon layer and a lower polysilicon layer.

3. The semiconductor device according to claim 2 , further comprising at least two memory shallow trench isolation (STI) structures disposed in the recess.

4. The semiconductor device according to claim 3 , wherein the non-volatile gate stack includes a floating gate composed of the lower polysilicon layer, and the floating gate is disposed between the two memory STI structures.

5. The semiconductor device according to claim 1 , further comprising at least one logic STI structure disposed in the logic region, wherein a top surface of the logic STI structure is higher than a top surface of the memory STI structures.

6. The semiconductor device according to claim 1 , further comprising:
a buffer layer covering a sidewall of the non-volatile gate stack but not disposed in the logic region; and
a spacer covering the surface of the buffer layer in the memory region and a sidewall of the logic gate stack in the logic region.

7. The semiconductor device according to claim 6 , wherein the buffer layer comprises oxide.

8. The semiconductor device according to claim 1 , wherein the logic gate stack comprises metal material.

9. The semiconductor device according to claim 1 , wherein a depth of the recess is about 500 to about 2500 angstroms.

10. The semiconductor device according to claim 1 , wherein the step height is about 200 to about 800 angstroms.

11. The semiconductor device according to claim 1 , wherein the non-volatile gate stack belongs to a non-volatile memory (NVM) cell, and the NVM cell is an electron tunnel oxide (ETOX) NVM cell or a silicon ONO silicon (SONOS) NVM cell.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Ching
• Chen Ko-Chi
• Wang Shen-De

Classifications

• H01L27/11529 Primary

  Electricity · mapped topic

• H01L27/11531

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/46 Primary

  with an inter-gate dielectric layer also being used as part of the peripheral transistor · CPC title